6T SRAM Cell Research Articles

Impact of Temperature and Process Corners on Read Bit Line of 8T-SRAM Cell for NOR, NAND Operations

SRAM reliability is one of the major concerns as it suffers from variations in Static Noise Margin with temperature variations, which degrades the performance. It needs attention due to the increasing impact of process corners, which are variations in parameters due to the switching properties of transistors. Since the SRAM is also used as in-memory computation, stability plays a significant role in the computation. In this manuscript, 8T-SRAM stability for NOR, NAND logic is presented at process corners: Fast NMOS-Fast PMOS (FF), Fast NMOS-Slow PMOS (FS), and Slow NMOS-Slow PMOS (SS), with changes in temperature and monte-carlo simulations are also performed to predict the probability of Read Bit Line (RBL) voltage. The results are obtained using Cadence Virtuoso Simulations at the 45 nm technology node and show that the RBL voltage deviates by 10–30 mV for every 25°C rise in temperature from −25oC to 125oC.

A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability

This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61×/1.33×/1.44×/1.63×/1.46×, and reduction in power consumption during read operation by 1.02×/1.55×/ 1.01×/1.81×/1.97× in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67×/1.71×/2.59×/1.45×/1.97×, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03×/1.01×/1.65×/1.54×/1.43×, and 1.42×/1.33×/1.41×/1.02×/1.62×, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Cryptography is crucial in embedded systems for safeguarding sensitive information, maintaining data integrity, and facilitating secure communication. L1 cache memory enhances overall performance by temporarily storing cryptographic keys. Post-quantum cryptography (PQC) focuses on creating algorithms that stay secure even against quantum computing threats. However, PQC doesn't fully protect against side-channel attacks (SCA). As IoT devices like wearable health monitors and industrial sensors become more widespread, the demand for lightweight cryptography increases to balance security with resource constraints. Yet, lightweight cryptography can face challenges, including reduced security and increased susceptibility to SCA due to smaller key sizes. Attackers can exploit power consumption patterns through side-channel attacks (SCA), such as Power Analysis, to extract these secret keys. Once a key is compromised, encrypted data becomes vulnerable. In cloud computing cache side-channel attacks take advantage of multiple virtual machines running simultaneously on the same hardware, enabling them to extract sensitive information from encryption processes. Although many SRAM cells have been designed in the literature, none offer complete security against SCA. This paper presents a new architecture for secure cache memory using a proposed 10T SRAM cell that secures all three cell operations (read, write, and hold) against SCA attacks. Additionally, this architecture also prevents half selection issue in cache memory. The security measure of proposed-10T cell is 97.19 % which is highest among all other cells and reliability measure is 82.03 %.The cell also offers highest hold stability of 421 mV along with good read stability and write ability of 220 mV and 334 mV respectively. The leakage of Proposed-10T cell is also less i.e., 13.56 pA. The Performance and Security Factor (PSF) is computed for all considered cells, encompassing various performance and security metrics. The normalized PSF (PSF)N of the Proposed-10T cell is 2.17, the highest among all cells considered for comparison. Therefore, the Proposed-10T cell architecture is fully secure against SCA and achieves better performance during cell operations.

Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node

Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations. Tools used: LTSpice v17 is the tool used to design the schematic circuits and to obtain the simulation results. The library file used to design the schematic is the 16nm technology node from the library of the Arizona State University’s Predictive Technology Model (ASU-PTM). Methods: To perform a comparative study of the 8T SRAM and 20T TICE, the schematic circuits were designed using the 16nm technology node in LTSpice. A baseline for the expected voltages of logic 0 and logic 1 is established before injecting errors at the sensitive voltage nodes of the circuit. The next step is to manually inject bit upsets at the crucial nodes of the memory cell to induce either a 0-1 upset or a 1-0 upset. The read/write operation is carried out along with the error injection to compare the error mitigation capacity of the circuits. Finally, the results are tabulated to prove that the 20T TICE is resilient to soft errors arising from exposure to high radiation. Results: During the normal operation of the 8T SRAM cell, the observed output voltage corresponding to logic 0 and logic 1 are 25mV and 780mV respectively. The voltage levels increased to 400mV during a 0-1 upset and dropped to 25mV during a 0-1 bit upset. This indicates that the cell is not reliable. In case of the 20T RHBD cell, the voltage levels for the normal operation were 5mV (logic 0) and 780mV (logic 1). The major improvement is shown in the case where the 20T TICE is injected with bit upsets, since it delivers a voltage of just 6mV during a 0-1 bit upset and maintains a voltage of 770mV during a 1-0 bit upset. Conclusion: The work performs the schematic designs for the comparison of the error mitigation capabilities of a 8T SRAM cell and a 20T TICE which is radiation hardened by design. The study proves that the 20T cell is capable of successfully mitigating both a 1-0 bit upset and a 0-1 bit upset

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices

Compute-in-memory has been increasingly appreciated by researchers as a well-suited hardware accelerator in convolutional neural networks (CNNs), because it can achieve low power consumption and high inference accuracy. This work presents a novel TD-CIM structure using:1) A Capacitor Charging scheme that uses Compact 8T Model for multiply-and-accumulate (MAC) Operations with serials inputs in Time Domain Level; 2) a new replicated bit-line time-domain converter (RBL-TDC) to achieve the quantization of the multiply-accumulate operations with high accuracy; 3) A 22 nm FD-SOI 16 Kb TD-CIM macro fabricated using foundry provided compact 8T-SRAM cells, which achieves normalized energy efficiency(EF) of 5816.5 TOPS/W, normalized area efficiency(64TOPS/mm2), and 8-bit weight for 8-bit serials inputs with 64 accumulations per cycle, as well as output precision(14b) in the MAC operation. This work also obtains an inference accuracy of 92.57 % on the VGG-16 network using the Cifar10 dataset over PVT variations.

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28 nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology

The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for creating schematic diagrams and layouts, while the ASSURA library is employed for conducting design rule checks (DRC) and layout versus schematic (LVS) comparisons to verify the alignment between the layout and the schematic. In the process, a low VDD of 1 V is taken for the design. The results shows that 10T SRAM is efficient in terms of read and write delay and power consumptions.

Evaluation of a Simplified Modeling Approach for SEE Cross-Section Prediction: A Case Study of SEU on 6T SRAM Cells

Electrical models play a crucial role in assessing the radiation sensitivity of devices. However, since they are usually not provided for end users, it is essential to have alternative modeling approaches to optimize circuit design before irradiation tests, and to support the understanding of post-irradiation data. This work proposes a novel simplified methodology to evaluate the single-event effects (SEEs) cross-section. To validate the proposed approach, we consider the 6T SRAM cell a case study in four technological nodes. The modeling considers layout features and the doping profile, presenting ways to estimate unknown parameters. The accuracy and limitations are determined by comparing our simulations with actual experimental data. The results demonstrated a strong correlation with irradiation data, without requiring any fitting of the simulation results or access to process design kit (PDK) data. This proves that our approach is a reliable method for calculating the single-event upset (SEU) cross-section for heavy-ion irradiation.

A novel single-ended 9T SRAM cell with write assist and decoupled read path for efficient low-voltage applications

A novel single-ended 9T SRAM cell with write assist and decoupled read path for efficient low-voltage applications

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

A Reliable and high performance Radiation Hardened Schmitt Trigger 12T SRAM cell for space applications

In the vacuum of space, alpha particles and cosmic radiation can cause the node data to be altered, leading to data loss. When a radiation particle hits a vulnerable point of the typical 6T static random access memory (SRAM) cell, it results in the alteration of the stored data within the cell, leading to a single-event upset (SEU). Traditional 6T SRAM cannot withstand the extreme conditions present in space. Hence, it is imperative to develop an SRAM that can endure these challenging space conditions. To address the impact of SEUs, a Radiation Hardened Schmitt Trigger 12 transistor (RHST12T) SRAM cell is proposed in this paper. To gauge the comparative effectiveness of the proposed cell, it is compared with other radiation hardened SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, and SRRD12T. Even if a radiation strike flips the node values, all of RHST12T sensitive nodes can recover their data. It shows up to 1.6×/45.32×/0.29 ×106× less read delay, write delay, and leakage power consumption, respectively as compared to other considered SRAM cells. It achieves up to 5.75×/3.09× better read and hold stability, respectively than the considered SRAM cells.