65-nm Complementary Metal Oxide Semiconductor Research Articles

Configurable in-memory computing architecture based on dual-port SRAM

In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner.

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

Embedded dynamic random-access memories (eDRAM) are widely used in the design of embedded systems for the safeguard of information during their operation. However, since these memories are installed in the same chip as the host system, it is crucial to consider their dimensioning. For this reason, in our work, the aspect ratio width and length (W/L) of complementary metal oxide semiconductor (CMOS) transistors inside 3-transistor logic cells (3T) is diversified to evaluate the effect on electrical behavior with area optimization through the figure of merit (FoM): power consumption-delay product of 8-bit memories with an operating frequency of 8.3 MHz, varying the aspect ratio of transistors inside the cell have been obtained 8.6f as lowest and 152.3f as highest FoM values. Those storage devices have been developed on 0.00085 mm2 using a 180-nm CMOS technology.

A 24−30 GHz 8-element dual-polarized 5G FR2 phased-array transceiver IC with 20.8-dBm TX OP1dB and 4.1-dB RX NFin 65-nm CMOS

This article presents an 8-element dual-polarized phased-array transceiver (TRX) front-end IC for millimeter-wave (mm-Wave) 5G new radio (NR). Power enhancement technologies for power amplifiers (PA) in mm-Wave 5G phased-array TRX are discussed. A four-stage wideband high-power class-AB PA with distributed-active-transformer (DAT) power combining and multi-stage second-harmonic traps is proposed, ensuring the mitigated amplitude-to-phase (AM-PM) distortions across wide carrier frequencies without degrading transmitting (TX) power, gain and efficiency. TX and receiving (RX) switching is achieved by a matching network co-designed on-chip T/R switch. In each TRX element, 6-bit 360° phase shifting and 6-bit 31.5-dB gain tuning are respectively achieved by the digital-controlled vector-modulated phase shifter (VMPS) and differential attenuator (ATT). Fabricated in 65-nm bulk complementary metal oxide semiconductor (CMOS), the proposed TRX demonstrates the measured peak TX/RX gains of 25.5/21.3 dB, covering the 24−29.5 GHz band. The measured peak TX OP1dB and power-added efficiency (PAE) are 20.8 dBm and 21.1%, respectively. The measured minimum RX NF is 4.1 dB. The TRX achieves an output power of 11.0−12.4 dBm and error vector magnitude (EVM) of 5% with 400-MHz 5G NR FR2 OFDM 64-QAM signals across 24−29.5 GHz, covering 3GPP 5G NR FR2 operating bands of n257, n258, and n261.

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Three-Stacked CMOS Power Amplifier to Increase Output Power With Stability Enhancement for mm-Wave Beamforming Systems

In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> /180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{1\,dB}}$</tex-math> </inline-formula> was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.

28-GHz Bidirectional RF CMOS Amplifier Employing Body-Effect Control

This letter presents a 28-GHz bidirectional amplifier that operates as a low-noise amplifier (LNA) and a drive amplifier in the receiver (RX) (forward) and transmitter (TX) (backward) modes, respectively. In the proposed design, the bidirectional operation is realized through supply switching (SS) by utilizing the symmetric structure of a complementary metal–oxide–semiconductor (CMOS) device. Additionally, the body voltage control of an n-type MOS (nMOS) device is applied to attain symmetric and enhanced performance in both the forward and backward operations. The proposed design was fabricated using the 65-nm CMOS process and primarily characterized in the 28-GHz band. It achieves a nearly identical performance in both the forward and backward modes.

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments

This paper presents a radiation tolerant charge-pump Phase-Locked Loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage-or dose-dependent charge injection and address the limitations of Enclosed Layout Transistors (ELTs) in the conventional drain switched charge-pump. The circuit has been processed in a 65nm Complementary Metal Oxide Semiconductor (CMOS) technology and has been experimentally verified with X-rays up to a total ionizing dose of 180 Mrad.

A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter

This paper presents a Tapered Tunable Transmission Line (Tapered TTL) phase shifter that achieves a higher area efficiency than conventional Tunable Transmission Line (TTL) phase shifters while maintaining the same phase shift range with similar insertion losses. A systematic methodology is provided for the optimum design of the proposed phase shifter to maximize its area efficiency while providing the desired phase shift range and satisfying the maximum allowed input/output return and insertion losses. To verify the efficacy of the proposed solution, an eleven-cell phase shifter is fabricated in a standard 65-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the measurement results are reported. The fabricated circuit provides a 180-degree phase shift over the frequency range of 16.5 to 31 GHz with an average insertion loss of 7.2 dB. The proposed design presents a 25 percent reduction in the chip area per unit delay in comparison to the conventional design with the same average insertion loss.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

An Inductorless 20-Gbaud Overshoot Suppression Modulator Driver Using Interleave Frequency Variant Feedback in 90-nm CMOS

An inductorless modulator driver with effective overshoot suppression and a large swing for high-speed optical communications is presented. A novel interleave frequency variant feedback (IFVF) technique is proposed, which employs active feedback loops with the RC degeneration. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> degeneration allows place the pole in the overall transfer function to shape the waveform for overshoot and ringing suppression. Using a 90-nm complementary metal oxide semiconductor (CMOS) technology, the driver achieves a maximum 3.4 Vpp differential output voltage swing. Clear eye diagrams for non-return to zero (NRZ) and pulse amplitude modulation 4-level (PAM4) signal formats can be obtained up to 32 Gb/s and 20 Gbaud, respectively. The circuit consumes a total power of 560 mW and occupies a core area of only 0.092 mm2.

A Silicon-Based Radio Platform for Integrated Edge Sensing and Communication Toward Sustainable Healthcare

Faced with COVID-19 and the trend of aging, it is demanding to develop an online health metrics sensing solution for sustainable healthcare. An edge radio platform owning the function of integrated sensing and communications is promising to address the challenge. Radar demonstrates the capability for noncontact healthcare with high sensitivity and excellent privacy protection. Beyond conventional radar, this article presents a unique silicon-based radio platform for health status monitoring supported by coherent frequency-modulated continuous-wave (FMCW) radar at Ku-band and communication chip. The radar chip is fabricated by a 65-nm complementary metal–oxide–semiconductor (CMOS) process and demonstrates a 1.5-GHz chirp bandwidth with a 15-GHz center frequency in 220-mW power consumption. A specific small-volume antenna with modified Vivaldi architecture is utilized for emitting and receiving radar beams. Biomedical experiments were implemented based on the radio platform cooperating with the antenna and system-on-chip (SoC) field-programmable gate array (FPGA) edge unit. An industrial, scientific, and medical (ISM)-band frequency-shift keying (FSK) communication chip in 915-MHz center frequency with microwatt-level power consumption is used to attain communications on radar-detected health information. Through unified integration of radar chip, management software, and communication unit, the integrated radio platform featuring −72-dBm sensitivity with a 500-kb/s FSK data rate is exploited to drastically empower sustainable healthcare applications.

Dual-Band CMOS Low-Noise Amplifier Employing Transformer-Based Band-Switchable Load for 5G NR FR2 Applications

This letter presents a dual-band complementary metal–oxide–semiconductor (CMOS) low-noise amplifier (LNA) for fifth-generation (5G) new radio (NR) frequency range 2 (FR2) applications. The proposed design utilizes a transformer-based band-switchable load to tune resonance conditions in the 26–30- and 37–40-GHz bands. Through ON–OFF control of the transformer functionality, the primary inductance can be adjusted with lesser quality-factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor) degradation compared to the conventional direct inductor switching approach. The proposed design is implemented using a 65-nm CMOS process. At 28 and 39 GHz, respectively, the gains of 13.7 and 13.1 dB, noise figures (NFs) of 3.8 and 4.1 dB, input 1-dB compression points of −15.2 and −16 dBm, and input third-order intercept points of −7.15 and −6.85 dBm are realized. The implemented design draws a bias current of 11.6 mA with a 1-V supply.

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

A D-Band Joint Radar-Communication CMOS Transceiver

A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band joint radar-communication complementary metal–oxide–semiconductor (CMOS) transceiver featuring a dual-function mode multiplexer, a power-combining PA with high output power, a current choking high-gain mixer, a two-point modulation (TPM) frequency-modulated continuous-wave (FMCW) digital phase-locked loop (PLL) with a dual-core DCO, and a wideband I/Q local oscillator (LO) generator is implemented in 28-nm CMOS technology. In the radar mode, the RF front end demonstrates 46-GHz bandwidth (BW), and the on-chip PLL/LO generated FMCW chirp achieves a BW of 30 GHz and a slope of 30 GHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{s}$ </tex-math></inline-formula> . In the communication mode, the transceiver including the analog baseband realizes 20-GHz BW, and the image rejection ratio (IRR) is better than 40 dB. The measured transmitter (TX) saturated output power is 13 dBm, and the output 1-dB compression point (OP1dB) is 8.3 dBm. The measured typical PLL phase noise is −111.3 dBc/Hz at a 1-MHz offset from an 11.69-GHz carrier frequency. The TX-to-RX over-the-air (OTA) modulation–demodulation measurement with QPSK and 16-QAM signals shows the error vector magnitude (EVM) of −16.5 and −19.7 dB, respectively.

A Dual-Mode Polarization Image Sensor Design Based on In-Pixel Dual-Band Metal Wire Grid for Trustworthy Sensing

In this article, we present the design of an on-chip polarization image sensor with a hardware root of trust (RoT) for trustworthy sensing provided by an interconnection metal-wire-grid (MWG) structure using a standard complementary-metal-oxide-semiconductor (CMOS) process. The proposed MWG structure features dual operation modes, which are polarization image sensing mode at the visible spectrum and physical unclonable function (PUF) mode at the near-infrared spectrum. By integrating the MWG on top of the photo-sensing pixel, the corresponding photocurrent is read out with a mainstream three-transistor-active-pixel-sensor (3T-APS). Moreover, prototype chips are fabricated using a 65-nm 1P8M CMOS process to validate the proposed design. For the polarization mode at 630 nm, the extinction ratio (ER) is measured to be 17 dB. For the PUF mode at 875 nm, the averaged unstable bits and bit error rate (BER) of 15 test chips are reported to be 3.5% and 0.29%, respectively. The responses generated in the PUF mode of the fabricated sensor chips also passed the widely adopted National Institute of Standards and Technology (NIST) and the autocorrelation function (ACF) randomness tests.

An maximum power point tracking interface circuit for low-voltage DC-type energy harvesting sources

This paper presents a maximum power point tracking (MPPT) interface circuit for low-voltage DC-type energy harvesting sources such as light and thermal energy. Most energy harvesting systems used in miniature-sized sensor systems require start-up circuits because the output voltages of small-sized energy transducers are very low and not enough to directly power electronic systems. The proposed interface circuit is driven directly by the low output voltages of small size energy transducers, eliminating the need for complex start-up circuitry. A simple MPPT controller with the fractional open-circuit voltage (FOCV) method is designed and fabricated in a 65-nm complementary metal oxide semiconductor (CMOS) process. Measurement results show that the designed circuit can track the MPP voltage even in the presence of the open-circuit voltage fluctuations and can operate properly at operating voltages as low as 0.3 V. The interface circuit achieves a peak power efficiency of 97.1% and an MPPT accuracy of over 98.3%.

A Compact On-Chip Pad Structure With an Embedded Capacitor for Broadband Millimeter-Wave Bond-Wire Interconnection

This article presents a compact on-chip pad structure with an embedded capacitor for millimeter-wave bond-wire interconnection, which is realized by 65-nm complementary metal–oxide–semiconductor (CMOS) process and able to compensate the parasitic inductance introduced by bonding wires. The proposed pad structure implemented by metal stacking is equivalent to an on-chip series capacitor. Moreover, a deep N-well structure is loaded at the bottom of the pad to reduce the parasitic pad-to-ground capacitance. This pad structure has been applied to the chip-to-chip interconnection with a measured minimum insertion loss (IL) of 2.179 dB and a measured 3-dB bandwidth of 11.9 GHz from 35.6 to 47.5 GHz. In addition, it has been applied to the chip-to-printed circuit board (PCB) interconnect ion with a measured one-sided loss of 1.7475 dB and a measured 3-dB bandwidth of 12 GHz from 22.7 to 34.7 GHz. Both applications using bond-wire interconnections prove that the proposed pad structure can compensate bond-wire inductance and realize broadband low-loss impedance matching.

A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.