Abstract
This paper presents a Tapered Tunable Transmission Line (Tapered TTL) phase shifter that achieves a higher area efficiency than conventional Tunable Transmission Line (TTL) phase shifters while maintaining the same phase shift range with similar insertion losses. A systematic methodology is provided for the optimum design of the proposed phase shifter to maximize its area efficiency while providing the desired phase shift range and satisfying the maximum allowed input/output return and insertion losses. To verify the efficacy of the proposed solution, an eleven-cell phase shifter is fabricated in a standard 65-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the measurement results are reported. The fabricated circuit provides a 180-degree phase shift over the frequency range of 16.5 to 31 GHz with an average insertion loss of 7.2 dB. The proposed design presents a 25 percent reduction in the chip area per unit delay in comparison to the conventional design with the same average insertion loss.
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