64-Mb DRAM Research Articles

A 99-mm/sup 2/ 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13-/spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mb DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7 W by adopting a low-power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multichip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder for portable HDTV codec system.

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAM's is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-Accuracy Defect-Free X-Ray Mask Technology

There are many material and processing options for building highly accurate defect-free X-ray masks that meet the 0.25-µ m and smaller lithography groundrules. IBM's path and rationale for reducing the key mask parameters of image size, image placement and defects is covered. For image size resolution and control, high voltage e-beam lithography (greater then 50 kV) is the preferred technique for X-ray masks. For tighter image placement control, special writing schemes that reduce the e-beam lithography systematic and random placement errors must be used. Special absorber electroplating conditions and thermal controls were implemented to control process-induced distortion. For tight defect control, identifying and eliminating sources of defect is key. Clearly, for IBM, most of the defect sources were process rather than foreign material related. Our defect reduction work has resulted in the fabrication of a fully functional 64-Mb DRAM (single chip) mask.

Open/folded bit-line arrangement for ultra-high-density DRAM's

An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F/sup 2/ memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel hierarchical approach for proximity effect correction in electron beam lithography

An efficient CAD pattern processing algorithm based on dose modulation technique is proposed for proximity effect correction calculation in electron beam (EB) lithography. The algorithm resolves a costly and lengthy computation during the pattern processing. First, the original pattern data with multiple-level cell hierarchy is reduced to pattern data with two-level cell hierarchy. Then, a zoning algorithm with dual-frame technique is introduced for realizing the hierarchical proximity correction calculation. Here, the zone is a region of pattern assembly to be proximity-corrected and the frame is a pattern reference region to incorporate the backscattering effects of electrons exposed on the frame into the zone data. The algorithm is applied to typical design layers of 64-Mb DRAM pattern data. The final EB data volume is greatly compacted by a factor of 22-150 compared with a conventional hierarchy-flattened method. The hierarchical approach is indispensable to the accurate proximity correction for next-generation high-density VLSIs. >

Investigation of SOI-like I-V characteristics for a 64-Mb DRAM SCC MOSFET with a buried drain

The MOSFET structure of a surrounding-high-capacitance cell (SCC) trench cell with a buried drain scaled down for 64-Mb DRAM applications has been studied using the device simulator MINIMOS. For this cell design, the depletion zones of the buried drain can pinch off the substrate at a sufficiently high drain bias. The resulting floating substrate causes sharply increased avalanche carrier generation similar to (but more severe than) the kink effects found in SOI structures. These effects limit the utility of this structure for small-geometry DRAM structures. The mechanism for the enhanced avalanche generation and its dependence on bias conditions and geometry have been studied, and pertinent design rules for punchthrough and pinchoff by the buried drain have been established. >

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10/sup 5/ times reliability improvement and a 0.3 approximately 1.8-V larger word-line voltage margin to write ONE data into the cell.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V/sub cc/), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V/sub cc/ DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V/sub cc/ of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3- mu m electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

UV-O/sub 3/ and dry-O/sub 2/: Two-step-annealed chemical vapor-deposited Ta/sub 2/O/sub 5/ films for storage dielectrics of 64-Mb DRAMs

A capacitor fabrication technique is developed to obtain an extremely thin Ta/sub 2/O/sub 5/ film with an effective SiO/sub 2/ film thickness of 2.8 nm (equivalent to 12 fF/ mu m/sup 2/) for use in a low-power 64-Mb DRAM. A two-step annealing process is used after deposition of the Ta/sub 2/O/sub 5/ film by thermal chemical vapor deposition (CVD). The first step is ozone (O/sub 3/) annealing with ultraviolet light irradiation, which is the most effective means of reducing leakage current. A model for explaining the effectiveness of the UV-O/sub 3/ annealing treatment is proposed. Excited oxygen atoms in the singlet state (/sup 1/D), which are generated selectively in the ozone gas irradiated by a mercury lamp, repair the oxygen vacancies existing in the as-deposited CVD-Ta/sub 2/O/sub 5/ film, resulting in a marked reduction of the film's leakage current. The second step is dry-O/sub 2/ annealing, which reduces the defect density of initial breakdown. Sufficient capacitance can be obtained while maintaining a low leakage current and sufficient step coverage for a 1.5-V supply-voltage 64-Mb DRAM having a high-aspect three-dimensional memory cell.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electron Beam Direct Writing Technology for 64-Mb DRAM LSIs

This paper describes the electron beam direct writing technology for 64-Mb DRAM LSIs including a resist process for 0.3-µm resolution, the prevention of the charging problem by a conducting polymer, and proximity effect correction by both the pattern classification method and the subsidiary exposure method. A large amount of pattern data is processed after dividing the whole chip data into peripheral circuits and 256-kb memory mats. An experimental 64-Mb DRAM LSI is fabricated by these technologies.

Ferroelectric materials for 64 Mb and 256 Mb DRAMs

The authors have studied the feasibility of using ferroelectric materials as the capacitor dielectric in the one-transistor memory cells for 64-Mb and 256-Mb DRAMs. They have performed an intensive literature search and analysis. They discuss the crystal structure of the materials reviewed, their hysteresis curve, temperature dependence of the spontaneous polarization, leakage current, dielectric breakdown, reliability, ageing, and fatigue. The authors examine the charge storage capacity in a 1-T DRAM cell and analyze a number of ferroelectric materials for their potential use as the dielectric in 64-Mb and 256-Mb DRAM capacitors, focusing on projected requirements for the electrical parameters and preferred material characteristics. Of the materials examined, those that appear to hold the greatest promise for 64-Mb and 256-Mb DRAMs are the paraelectric phase compositions of (Pb,La)TiO/sub 3/ (PLT) and (Pb,La)(Zr,Ti)O/sub 3/ (PLZT). Pb(Mg,Nb)O/sub 3/ (PMN) is also attractive because it is paraelectric, but it may not be able to achieve the required charge densities when deposited as a thin film. >

Two-step annealing technique for leakage current reduction in chemical-vapor-deposited Ta/sub 2/O/sub 5/ film

A capacitor technology developed to obtain extremely thin Ta/sub 2/O/sub 5/ dielectric film with an effective SiO/sub 2/ film thickness down to 3 nm (equivalent to 11 fF/ mu m/sup 2/) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta/sub 2/O/sub 5/ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O/sub 3/) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O/sub 2/) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps. >