4H-SiC Metal Semiconductor Field Effect Transistor Research Articles

Improved multi-recessed p-buffer 4H–SiC metal-semiconductor field-effect transistor with high power added efficiency

Based on the Multi-Recessed p-Buffer (MRB) Metal-Semiconductor Field-Effect Transistor (MESFET), this paper presents an Improved MRB 4H–SiC MESFET (IMRB MESFET) with high Power-Added Efficiency (PAE). The proposed structure has optimized recessed buffer layer from gate to drain. While maintaining excellent Radio Frequency performance, the maximum power density and PAE are greatly improved. The simulation results show that compared with MRB MESFET, the saturated drain current of IMRB MESFET is increased by 91.1%, the transconductance is increased by 15.5%, the Pmax is increased by 32.4%, and the PAE is increased by 40.29%. In summary, the IMRB MESFET is not only simple to manufacture, but also increases the energy conversion efficiency.

Improved 4H-SiC Metal–Semiconductor Field-Effect Transistors with Double-Symmetric-Step Buried Oxide Layer for High-Energy-Efficiency Applications

Improved 4H-SiC Metal–Semiconductor Field-Effect Transistors with Double-Symmetric-Step Buried Oxide Layer for High-Energy-Efficiency Applications

Improved DRUS 4H-SiC MESFET with High Power Added Efficiency.

A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

An Improved 4H-SiC MESFET with a Partially Low Doped Channel.

An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

Novel 4H-SiC MESFET with modified depletion region by dual well for high-current applications

We describe herein a 4H-SiC metal---semiconductor field-effect transistor (MESFET) with a novel dual well in the buffer layer. The key idea is to change the channel thickness to decrease the hole concentration and modify the depletion region shape and drain current path in the channel. In the proposed structure, a dual well is created in the buffer layer exactly under the gate. We call this structure the dual-well MESFET (DW-MESFET). The drain current of the proposed structure increases by 34.7 % compared with the conventional structure (C-MESFET) due to the change in channel thickness and modification of the depletion region and drain current path. Also, the maximum power density ($$P_{\mathrm{max}}$$Pmax) and the direct-current (DC) transconductance ($$g_{\mathrm{m}}$$gm) of the DW-MESFET increase by 45.23 and 72.5 %, respectively, in comparison with the C-MESFET structure. Hence, the proposed structure can be used for high-current and high-power applications.

A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

In this paper, a novel symmetrical structure (SS) of 4H---SiC metal semiconductor field effect transistor (MESFET) as an effective way to improve the breakdown voltage is presented. The key idea in this work is to improve the breakdown voltage, maximum output power density, and frequency parameters of the device using a symmetrical structure with recessed gate. The SS-MESFET modifies the electric field in the drift layer significantly. The influence of the SS-MESFET on the saturation current, breakdown voltage $$(\hbox {V}_{\mathrm{BR}})$$(VBR), and small-signal characteristics of the SS-MESFET are studied by numerical device simulation. Using two-dimensional device simulation, we demonstrate that the breakdown voltage $$(\hbox {V}_{\mathrm{BR}})$$(VBR) improved by factors 2.5 and 3.3 in comparison with an asymmetrical conventional MESFET structure (AC-MESFET) and a symmetrical conventional MESFET structure (SC-MESFET), respectively. Also, the maximum output power density $$(\hbox {P}_{\mathrm{max}})$$(Pmax) improved about by 93 and 250 % in comparison with the AC-MESFET and SC-MESFET structures, respectively. So, the SS-MESFET shows the superior maximum available gain (MAG), unilateral power gain (U), and current gain $$(\hbox {h}_{12})$$(h12) which is presenting the proposed structure is more suitable device for high power microwave applications.

A novel 4H–SiC MESFET with clival gate

In this paper, a novel 4H–SiC metal semiconductor field effect transistor (MESFET) with a clival gate structure (CG-MESFET) is proposed. The drain current (ID) and the breakdown voltage (VB) are simulated and compared to the traditional double-recessed gate 4H–SiC MESFET (DR-MESFET). The results indicate that the drain current (ID) of the CG-MESFET transforms with the change of end point of clival gate (EPCG), and it reaches to a maximum value about 545mA when EPCG is at 1/2 of whole gate, thus, the drain current (ID) has a much greater increase than that of the DR-MESFET. The CG-MESFET has the advantages of high breakdown voltage (VB) that is increased by 15% and superior DC performances over the DR-MESFET.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Dependence of the Breakdown Voltage of 4H-SiC MESFET’s on the Field Plate and Step-Channel

The breakdown mechanism of the 4H-SiC metal-semiconductor field effect transistor (4H-SiC MESFET) at a large drain bias is explored and the dependence of breakdown voltage on the field-plate and the step-channel is investigated by simulation. The results revealed that the breakdown occurs at the corner of the gate near to the drain. The channel step and the field-plate length have sensitive effect on the breakdown voltage. The breakdown characteristics are improved since the electric field peak is lowered at breakdown point in the step-channel and field-plate structures. The largest breakdown voltage can be achieved by optimizing the field-plate length.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

In this paper, we present the unique features exhibited by a novel double-recessed 4H-SiC Metal–Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (VBR) and the drain saturation current (IDsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (Pmax) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (fT) of 15GHz and the maximum oscillation frequency (fMax) of 135GHz for 4H-SiC FMR-MESFET is obtained compared to 13GHz and 120GHz for that of the CDR-MESFET and the minimum figure noise (Fmin) decreased as a result of reducing gate–drain and gate–source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Fabrication and Characteristics of Ion-implanted 4H Silicon Carbide Metal-Semiconductor Field-Effect Transistors on a P-Type Epilayer

The methods for the design and fabrication of ion-implanted 4H silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs) have been studied. The N-well regions are formed by three-fold (Sample A) and four-fold (Sample B) nitrogen ionimplantation on Si-face P-type epilayers with a net accept doping concentration of 6.5×10^15 cm^(-3) grown at american corporation Cree. The layout with testing structures has been designed. The locations of the peak concentration and the longitudinal straggles of the implanted ions are simulated by the Monte Carlo simulator TRIM. The box-like profile for the implantation layer is calculated by the Gauss expression. According to the structure of the device and the energy band for the implantation layer, the theoretical equation of the channel depth for the ion-implantation technique is given and calculated. The processes used to determine the implantation energies and doses are discussed. The experiment for ion-implanted 4H-SiC MESFETs is performed. The Ohmic and Schottky contact metals are annealed Ni/Cr alloy and Ti/Pt double-metal layers, respectively, and the pad metallization is Au. The performance of the current-voltage characteristics of the two samples of ion-implanted 4H-SiC MESFETs has been given at the end.

A novel 4H–SiC MESFET with modified channel depletion region for high power and high frequency applications

In this paper, a novel 4H–SiC metal semiconductor field effect transistor (MESFET) with modified depletion region is introduced. The key idea in this work is modifying the depletion region in the channel for improving the electrical performances. The proposed structure consists of upper and lower gates. Also, the lower gate is divided into a number (N) of smaller step-shaped sections. Therefore, we have called the proposed structure multiple-recessed 4H–SiC MESFET (MR-MESFET). DC and RF characteristics of the MR-MESFET structure with various lower gate segments are analyzed by 2D numerical simulation. The simulated results show that as the number of the lower gate sections increases, the channel depletion region is modified and the drain current ( I D) enhances. Also, by increasing the number of the lower gate sections, the breakdown voltage ( V BR) enhances, too. Improvement of the I D and V BR leads to a further increase in the output power density of the device. Also, cut-off frequency ( f T), maximum oscillation frequency ( f max), and maximum available gain (MAG) improvements are achieved for the MR-MESFET structure with further number of the lower gate sections. The results show that the MR-MESFET structure with higher number of the lower gate segments has superior electrical characteristics and performances in comparison with the MR-MESFET structure with fewer number of the lower gate sections.

A novel double-recessed 4H-SiC MESFET with partly undoped space region

In this paper, a novel double-recessed 4H-SiC metal semiconductor field effect transistor (MESFET) with partly undoped space region (DRUS-MESFET) is introduced. The key idea in this work is to improve the DC and RF characteristics of the device by introducing an undoped space region. Using two-dimensional and two-carrier device simulation, we demonstrate that breakdown voltage ( V BR) increases from 109 V in conventional double recessed MESFET (DR-MESFET) structure to 144.5 V in the DRUS-MESFET structure due to the modified channel electric field distribution of the proposed structure. The maximum output power density of the DRUS-MESFET structure is about 25.4% larger than that of the DR-MESFET structure. Furthermore, lower gate–drain capacitance ( C GD), higher cut-off frequency ( f T), larger maximum available gain (MAG), and higher maximum oscillation frequency ( f max) are achieved for the DRUS-MESFET structure. The results show that the f max and f T of the proposed structure improve 95.6% and 13.07% respectively, compared with that of the DR-MESFET structure. Also, the MAG of the DRUS-MESET is 4.5 dB higher than that of the DR-MESFET structure at 40 GHz. The results show that the DRUS-MESFET structure has superior electrical characteristics and performances in comparison with the DR-MESFET structure.

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors (MESFETs) with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.

Parameter analysis for gate metal-oxide-semiconductor structures of ion-implanted 4H silicon carbide metal-semiconductor field-effect transistors

From the theoretical analysis of the thermionic emission model of current-voltage characteristics, this paper extracts the parameters for the gate Schottky contact of two ion-implanted 4H-SiC metal-semiconductor field-effect transistors (sample A and sample B for three and four times multiple ion-implantation channel region respectively) fabricated in the experiment, including the ideality factor, the series resistance, the zero-field barrier height, the interface oxide capacitance, the interface state density distribution, the neutral level of interface states and the fixed space charge density. The methods to improve the interface of the ion-implanted Schottky contact are given at last.

Transient Response of Charge Collection by Single Ion Strike in 4H-SiC MESFETs

The radiation damage of 4H-SiC Metal Semiconductor Field Effect Transistors (MESFETs) due to gamma rays was studied. The threshold voltage and Schottky property of gate contact varied only slightly after absorbed dose of 10.4 MGy(SiC). In addition, the transient response of charge collection was studied by using transient ion beam induced current (TIBIC) system. It was found that the collected charge was several orders of magnitudes higher than the charge induced in SiC by direct ionization. The most likely explanation of the enhanced charge collection was the bipolar and the channel modulation effects.

Physical simulations and experimental results of 4H-SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H-SiC metal semiconductor field effect transistors (MESFETs) on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H-SiC MESFETs with 100 μm gate periphery. At 30 V drain voltage, the maximum current density is 440 mA/mm and the maximum transconductance is 33 mS/mm. For the continuous wave (CW) at a frequency of 2 GHz, the maximum output power density is measured to be 6.6 W/mm, with a gain of 12 dB and power-added efficiency of 33.7%. The cut-off frequency (fT) and the maximum frequency (fmax) are 9 GHz and 24.9 GHz respectively. The simulation results of fT and fmax are 11.4 GHz and 38.6 GHz respectively.

Model and analysis of drain induced barrier lowering effect for 4H-SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H-SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H-SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage VDS and channel doping concentration ND, thus providing a good basis for the design and modelling of short channel 4H-SiC MESFETs device.

Asymmetric 3D tri-gate 4H-SiC MESFETs with a recessed drain drift region

An improved asymmetric 3D tri-gate 4H-SiC metal–semiconductor field effect transistor with a recessed drain drift region was proposed in order to improve the power and frequency performance of the device. The dc and RF electrical characteristics of the proposed structure were studied in detail by numerical simulation. The simulated results showed that the maximum theoretical output power density of the proposed structure is about 36% larger than that of the published symmetric 3D tri-gate structure due to significant improvement of saturation drain current and breakdown voltage. The cut-off frequency (fT) and the maximum oscillation frequency (fmax) of the proposed structure are 20.6 GHz and 82.4 GHz compared to 16.1 GHz and 55.9 GHz of those of the published 3D tri-gate structure, respectively.