4H-SiC Interface Research Articles

Detection and Electrical Characterization of Defects at the SiO<sub>2</sub>/4H-SiC Interface

Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (ECEit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Electrical Properties and Gas Sensing Characteristics of the Al<sub>2</sub>O<sub>3</sub>/4H SiC Interface Studied by Impedance Spectroscopy

Using impedance spectroscopy (IS) for characterization of the electrical properties and gas sensing characteristics of Al2O3/4H-SiC (MOS) structures, insight on the capacitive and resistive contributions in the interfacial region of the MOS structures is obtained. Applying DC bias voltages between accumulation and depletion (corresponding to the interfacial region) allows investigation of the voltage shift of the capacitance versus voltage (CV) curve at different temperatures and atmospheres. This voltage shift forms the basis to use the MOS structure as a gas sensor. The MOS capacitance, as extracted from IS data, is different from the one obtained using CV measurements, due to the ability of distinguishing the resistive contribution (using IS). Voltage shifts between 1 and 2 V are clearly revealed during exposure to hydrogen and oxygen, and this shift exhibits a long-term stability of operation at temperatures up to 500°C. Hence, Al2O3 exhibits great promise as a gate dielectric in MOS-based gas detecting devices for use at elevated temperatures.

Fabrication of 1.2kV, 100A, 4H-SiC(0001) and (000-1) Junction Barrier Schottky Diodes with Almost Same Schottky Barrier Height

It is known that a Schottky barrier height (b) of metal/C-face 4H-SiC Schottky barrier diode (SBD) differ from b of metal/Si-face 4H-SiC SBD. Furthermore, b of metal/4H-SiC SBD varies with annealing temperature. We fabricate 0.231mm2 SBD with Ti/SiC interface using Si-face and C-face 4H-SiC. These SBDs are annealed at several temperatures after a formation of the Ti/SiC interface. As a result, b of Ti/C-face 4H-SiC interface annealed at 400 oC is nearly equal to b of Ti/Si-face 4H-SiC interface annealed at 500 oC and the n-values of these SBDs are nearly equal to the ideal value (unity). Using that annealing condition, we fabricated 25mm2 junction barrier Schottky (JBS) diodes with Ti/SiC interface on Si-face and C-face 4H-SiC epitaxial substrate. b of Si-face and C-face JBS diodes are 1.26eV and 1.24eV, respectively. The leakage currents for both Si-face and C-face JBS diodes are less than 1mA/cm2. The current of 100A is obtained at the forward bias voltage of 1.95V and 2.16V for the Si-face JBS and the C-face JBS.

Generation of Amorphous SiO<sub>2</sub>/SiC Interface Structure by the First-Principles Molecular Dynamics Simulation

The performance of SiC MOSFET devices to date is below theoretically expected performance levels. This is widely considered to be attributed to defect at the SiO2/SiC interface that degrade the electrical performance of the device. To analyze the relationship between defect structures near the interface and electrical performances, advanced computer simulations were performed. A slab model using 444 atoms for an amorphous oxide layer on a 4H-SiC (0001) substrate was made by using first-principles molecular dynamic simulation code optimized for the Earth-Simulator. Simulated heating and rapid quenching was performed for the slab model in order to obtain a more realistic structure and electronic geometry of a-SiO2/4H-SiC interface. The heating temperature, the heating time and the speed of rapid quenching were 4000 K, 3.0 ps and -1000 K/ps, respectively. The interatomic distance and the bond angles of SiO2 layers after the calculation are agree well with the most probable values of bulk a-SiO2 layers, and no coordination defects were observed in the neighborhood of SiC substrate.

XPS Study of the Electronic Properties of the Ce/4H-SiC Interface, and the Formation of the SiO<sub>2</sub>/Ce<sub>2</sub>Si<sub>2</sub>O<sub>7</sub>/4H-SiC Interface Structure upon Oxidation

The deposition and annealing in ultra high vacuum (UHV) of 5-6 monolayers (ML) of cerium on clean reconstructed Si-face 4H-SiC (0001) is studied by x-ray photoemission spectroscopy (XPS). Band bending as a function of annealing was studied by shifts of the bulk peak contribution in the C1s and Si2p spectra relative to the clean reconstructed surface. Additional datapoints for Schottky barrier formation on 4H-SiC are thus obtained by the low work function rareearth metals, and presented in the framework of the metal-induced-gap states and electronegativity model. A Ce/CeSi2-x/4H-SiC interface alloy forms by annealing to 850-1050oC. Kinetic information from the oxidation of the Ce/CeSi2-x/4H-SiC interface alloy is also reported. In particular, a SiO2- x/Ce-Si mixed oxide/4H-SiC forms upon oxidation. The shift of the C1s SiC-bulk-peak towards higher binding energies upon oxidation indicates that the mixed Ce-Si oxide interface layer appears to passivate the near Fermi-level 4H-SiC interface states at least as well as SiO2, and are expected to modify the electrical interface characteristics.

A strong reduction in the density of near-interface traps at the SiO2∕4H-SiC interface by sodium enhanced oxidation

This paper demonstrates how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2∕4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1–10cm2∕Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these near-interface traps resulting in high inversion channel mobility of 150cm2∕Vs in such transistors. Sodium is incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during the formation of the SiC∕SiO2 interface.

Electronic structure and band alignment at the HfO2∕4H-SiC interface

To evaluate the potential of HfO2 as a gate dielectric in SiC power metal-oxide-semiconductor field effect transistors (MOSFETs), the band alignment at the HfO2∕4H-SiC interface was determined by x-ray photoelectron spectroscopy (XPS) measurements and first-principles calculations using density functional theory (DFT). For XPS studies, HfO2 films were grown on 4H-SiC (0001) by a thermal atomic layer deposition process. A valence band offset of 1.74eV and a conduction band offset of 0.70eV were determined based on the valence band and core-level spectra. DFT simulations of the Si-terminated 4H-SiC (0001) surface found a 1×1 relaxed structure whereas simulations of the C-terminated surface observed a 2×1 reconstruction to form C–C dimers. We studied two m-HfO2∕4H-SiC (0001) supercells based on these surfaces and valence band offset values of 2.09 and 1.47eV, and conduction band offset values of 0.35 and 0.97eV, respectively, were predicted. The consistently low conduction band offset may not provide an adequate barrier height for electron injection from the substrate and further electrical studies are necessary to determine the viability of integrating HfO2 in SiC power MOSFETs.

Nitrogen and Hydrogen Induced Trap Passivation at the SiO<sub>2</sub>/4H-SiC Interface

Post-oxidation anneals that introduce nitrogen at the SiO2/4H-SiC interface have been most effective in reducing the large interface trap density near the 4H-SiC conduction band-edge for (0001) Si face 4H-SiC. Herein, we report the effect of nitridation on interfaces created on the (11 20) a-face and the (0001) C-face of 4H-SiC. Significant reductions in trap density (from >1013 cm-2 eV-1 to ~ 1012 cm-2 eV-1 at EC-E ~0.1 eV) were observed for these different interfaces, indicating the presence of substantial nitrogen susceptible defects for all crystal faces. Annealing nitridated interfaces in hydrogen results in a further reduction of trap density (from ~1012 cm-2 eV-1 to ~5 x 1011 cm-2 eV-1 at EC-E ~0.1 eV). Using sequential anneals in NO and H2, maximum field effect mobilities of ~55 cm-2 V-1s-1 and ~100 cm-2 V-1s-1 have been obtained for lateral MOSFETs fabricated on the (0001) and (11 20) faces, respectively. These electronic measurements have been correlated to the interface chemical composition.

Electronic properties of the Ce∕4H-SiC interface studied by x-ray photoemission spectroscopy

The deposition and annealing in ultrahigh vacuum of 5–6 ML (monolayers) of cerium on clean reconstructed Si-face 4H-SiC (0001) are studied by x-ray photoemission spectroscopy and low-energy electron diffraction. Band bending as a function of annealing was studied by shifts of the bulk peak contribution in the C 1s and Si 2p spectra relative to the clean reconstructed surface. Silicide formation was studied by low binding energy components in the C 1s and Si 2p spectra. A large relative upward band bending of 0.3–0.4eV takes place upon deposition of Ce on 4H-SiC at room temperature. Upon annealing to 350°C, a disordered CeSixCy interface layer forms, as observed from chemically shifted components in the Si 2p and C 1s spectra. Annealing to 600°C causes the interface to become CeSi2−x, and carbon desorbs from the interface. A maximum relative band bending of 0.6eV is observed from 400to600°C. Further heating of the sample to 850–1000°C results in a relative total upward band bending of approximately 0.4eV and a relatively sharp CeSi2−x peak in the Si 2p spectrum. SiC bulk bonds appear not to be broken and it is found that a Ce overlayer terminates the layer, with a cerium silicide layer at the interface.

Defect layer in SiO 2–SiC interface proved by a slow positron beam

The structure of the SiO 2–4H-SiC interface layer produced by dry oxidation has been studied by positron annihilation spectroscopy using slow positron beams. From Doppler broadening measurements, the interface layer was clearly distinguished from the SiO 2 and SiC layers and was observed to be defective. At the interface layer, a single long positron lifetime of 451 ps, which is close to the second lifetime in the SiO 2 layer, was obtained, thus suggesting that the structure of the interface layer resembles an amorphous SiO 2 network. A comparison was made between the obtained electron momentum distribution at the interface layer and the theoretical calculation. It was found that positrons annihilate with oxygen valence electrons. By annealing after the oxidation, the annihilation probability of the positrons with oxygen valence electrons and the number of interface traps decreased in the same temperature range, thus suggesting a correlation between interface traps and positron annihilation sites.

A Comparison between SiO<sub>2</sub>/4H-SiC Interface Traps on (0001) and (11-20) Faces

We present thermally stimulated current (TSC) measurements made on metal-oxide-semiconductor (MOS) structures fabricated on off-axis (0001) or on-axis (1120) face n-type 4H-SiC with wet or dry oxid ...

Effect of nitric oxide annealing on the interface trap density near the conduction bandedge of 4H–SiC at the oxide/(112̄0) 4H–SiC interface

Nitric oxide postoxidation anneal results in a significant decrease of defect state density (Dit) near the conduction bandedge of n-4H–SiC at the oxide/(112̄0) 4H–SiC interface. Comparison with measurements on the conventional (0001) Si-terminated face shows a similar interface state density following passivation. Medium energy ion scattering provides a quantitative measure of nitrogen incorporation at the SiO2/SiC interface.

Effect of process variations and ambient temperature on electron mobility at the SiO/sub 2//4H-SiC interface

We report the effect of processing variables on the inversion layer electron mobility of (0001)-oriented 4H-SiC n-channel MOSFETs. The process variables investigated include: i) implant anneal temperature and ambient; ii) oxidation procedure; iii) postoxidation annealing in nitric oxide (NO); iv) type of gate material, and v) high-temperature ohmic contact anneal. Electron mobility is significantly increased by a postoxidation anneal in NO, but other process variations investigated have only minor effects on the channel mobility. We also report the temperature dependence of electron mobility for NO and non-NO annealed n-channel MOSFETs.

A Formation of SiO2/4H-SiC Interface by Oxidizing Deposited Poly-Si and High Temperature Hydrogen Annealing

ABSTRACTA formation of SiO2/4H-SiC interfaces by oxidizing deposited poly-Si on a 4H-SiC substrate and high temperature hydrogen annealing at low pressure ( 8.5×102 Pa ) has been investigated. The oxidation rate of deposited poly-Si was approximately 100 times faster than that of a SiC. Hydrogen annealing more effectively reduced the flat band voltage shift ( ΔVfb ) of the 4H-SiC MOS structure than argon and vacuum annealing. Moreover, the good SiO2/4H-SiC interface was formed because ΔVfb decreased as the oxidation temperature increased.