3D Packaging Research Articles

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.

Simultaneous measurements of top surface and its underlying film surfaces in multilayer film structure

With the growth of 3D packaging technology and the development of flexible, transparent electrodes, the use of multilayer thin-films is steadily increasing throughout high-tech industries including semiconductor, flat panel display, and solar photovoltaic industries. Also, this in turn leads to an increase in industrial demands for inspection of internal analysis. However, there still remain many technical limitations to overcome for measurement of the internal structure of the specimen without damage. In this paper, we propose an innovative optical inspection technique for simultaneous measurements of the surface and film thickness corresponding to each layer of multilayer film structures by computing the phase and reflectance over a wide range of wavelengths. For verification of our proposed method, the sample specimen of multilayer films was fabricated via photolithography process, and the surface profile and film thickness of each layer were measured by two different techniques of a stylus profilometer and an ellipsometer, respectively. Comparison results shows that our proposed technique enables simultaneous measurements of the top surface and its underlying film surfaces with high precision, which could not be measured by conventional non-destructive methods.

Parameter analysis on the ultrasonic TSV-filling process and electrochemical characters

As one of the key technologies in 3D packaging, through silicon via (TSV) interconnection technology has become a focus recently. In this paper, an electrodeposition method for TSV filling with the assistance of ultrasound and additives are introduced. Two important parameters i.e. current density and ultrasonic power are studied for TSV filling process and electrochemical properties. It is found that ultrasound can improve the quality of TSV-filling and change the TSV-filling mode. The experimental results also indicate that the filling rate enhances more significantly with decreasing current density under ultrasonic conditions than under silent conditions. In addition, according to the voltammetry curve, the increase of ultrasonic power can significantly increase the current density of cupric reduction, and decrease the thickness of diffusion layer. So that the reduction speed of copper ions is accelerated, resulting in a higher TSV-filling rate.

Consequences of high-frequency operation on EUV source efficiency

A potential problem of future extreme ultraviolet (EUV) sources, required for high volume manufacture regimes, can be related to the contamination of the chamber environment by products of preceding laser pulse/droplet interactions. Implementation of high, 100 kHz and higher, repetition rate of EUV sources using Sn droplets ignited with laser pulses can cause high accumulation of tin in the chamber in the form of vapor, fine mist, or fragmented clusters. In this work, the effects of the residual tin accumulation in the EUV chamber in dependence on laser parameters and mitigation system efficiency were studied. The effect of various pressures of tin vapor on the CO2 and Nd:YAG laser beam propagation and on the size, the intensity, and the resulting efficiency of the EUV sources was analyzed. The HEIGHTS 3D package was used for this analysis to study the effect of residual background pressure and spatial distribution on EUV photon emission and collection. It was found that background pressure in the range of 1–5 Pa does not significantly influence the EUV source produced by CO2 lasers. A larger volume with this pressure condition, however, can reduce the efficiency of the source. However, an optimized volume of mix with proper density could increase the efficiency of the sources produced by CO2 lasers.

Analysis on annealing-induced stress of blind-via TSV using FEM

Copper-filled through silicon via (TSV) is a promising material owing to its application in high-density three-dimensional (3D) packaging. However, in TSV manufacturing, thermo-mechanical stress is induced during the annealing process, often causing reliability issues. In this paper, the finite element method is employed to investigate the impacts of via shape and SiO2 liner uniformity on the thermo-mechanical properties of copper- filled blind-via TSV after annealing. Top interface stress analysis on the TSV structure shows that the curvature of via openings releases stress concentration that leads to ~60 MPa decrease of normal stresses, σxx and σyy, in copper and ~70 MPa decrease of σxx in silicon. Meanwhile, the vertical interface analysis shows that annealing-induced stress at the SiO2/Si interface depends heavily on SiO2 uniformity. By increasing the thickness of SiO2 linear, the stress at the vertical interface can be significantly reduced. Thus, process optimization to reduce the annealing-induced stress becomes feasible. The results of this study help us gain a better understanding of the thermo-mechanical behavior of the annealed TSV in 3D packaging.

Investigation of Au/Si Eutectic Wafer Bonding for MEMS Accelerometers

Au/Si eutectic bonding is considered to BE a promising technology for creating 3D structures and hermetic packaging in micro-electro-mechanical system (MEMS) devices. However, it suffers from the problems of a non-uniform bonding interface and complex processes for the interconnection of metal wires. This paper presents a novel Au/Si eutectic wafer bonding structure and an implementation method for MEMS accelerometer packaging. The related processing parameters influencing the Au/Si eutectic bonding quality were widely investigated. It was found that a high temperature of 400 °C with a low heating/cooling rate of 5 °C/min is crucial for successful Au/Si eutectic bonding. High contact force is beneficial for bonding uniformity, but the bonding strength and bonding yield decrease when the contact force increases from 3000 to 5000 N due to the metal squeezing out of the interface. The application of TiW as an adhesion layer on a glass substrate, compared with a commonly used Cr or Ti layer, significantly improves the bonding quality. The bonding strength is higher than 50 MPa, and the bonding yield is above 90% for the presented Au/Si eutectic bonding. Furthermore, the wafer-level vacuum packaging of the MEMS accelerometer was achieved based on Au/Si eutectic bonding and anodic bonding with one process. Testing results show a nonlinearity of 0.91% and a sensitivity of 1.06 V/g for the MEMS accelerometer. This Au/Si eutectic bonding process can be applied to the development of reliable, low-temperature, low-cost fabrication and hermetic packaging for MEMS devices.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore’s Law. Especially in the last decade an ever-increasing component integration on SoC’s has driven cost scaling and will continue to do so while approaching the IoT and wearable device area. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

Smart and innovative products are using the convergence of ubiquitous sensing and the communication by the internet. The so called Internet of Things/Everything (IoT/IoE) emerges from the traditional computing and mobile market and impacts every era in humans’ lives. Moore’s Law is the driver of these innovations in increasing component integration on SoC’s to deliver the right combination of performance, power, and cost to match the appropriated application. To continue to create compelling products, it will increasingly require all advancements and differentiations, more directly linking the CMOS-VLSI scaling to the integrated circuits; in an era where future systems may be different than the computers we are familiar with. A large variety of emerged technology concepts especially in the communication and sensor area as well as non-volatile memories will converge with the well-established VLSI-CMOS technology. The main requirements on the single semiconductor device and technologies are lowest leakage at lowest voltage operation at the minimum cost. Differentiated technologies such as 22nm and 12nm Fully Depleted Silicon on Insulator (FDSOI), common partially depleted SOI (PDSOI) RF as well as novel non-volatile memory concepts are entering the markets. Furthermore, SoC innovations will focus on 3D multi-die package integrations on system level to growth technologies into the Internet of Everything area. Planar CMOS devices especially in 28nm and 20nm are currently the mostly used technologies for mass production microprocessors and SoC’s since it’s at an optimized spot of cost and performance. Over the last decades new processing techniques as well as new materials have been introduced such as strained Si, high-k metal gate and ultra-low-k. With the non-manufacturable arrival of EUV lithography integration techniques such as double and quadruple patterning, self aligned contacts; air-gap interconnects as well as new materials are needed for VLSI technologies of 7nm and beyond. 3D FinFET devices as well as new device architectures are required to continue an over-scaling in order to maintain the historical Moore’s Law to overcome the increased cost per gate. Simultaneously, the effort on variation reduction, performance and yield improvements increases exponentially for the design and manufacturing community. To keep pace with the technology over-scaling advanced techniques and solutions on the design and process integration as well as manufacturing processes are necessary. Reducing all parasitic resistances and capacitances is key for technologies below 7nm to gain in further SoC scaling while maintaining its performance level. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. The FDSOI technology is a real independent multi-gate technology which can span an infinite VTH space for any circuit design. In addition it’s well suited for low and lowest power applications as well as RF, mmWave, analog and mixed Signal SOC’s. Since it’s a planer technology, process and technology elements from previous nodes can be transformed into this novel architecture. With its diffusion less concept scaling is possible down to the 12nm technology node while maintaining the lowest cost trend by saving up to 30% fewer mask steps. The performance produces NFET (PFET) drive currents of up to 910μA/µm (856μA/µm) at 0.8V and 100nA/µm IOFF. For ultra-low power applications, it offers low-voltage operation down to 0.4V Vmin. Ultra-low leakage devices serve up to 1pA/µm IOFF and body-biasing can be used to actively trade-off power and performance. RF/Analog characteristics are achieved including high fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for NFET and PFET, respectively. The high fMAX extends the capabilities to 5G and mmWave (>24GHz) RF applications. Implementing an increased amount of sub-systems like graphic, video, TV, RF applications, sensor interfaces etc. challenges occur on I/O interface components and sub-system scaling. What once was 5-15% of a SoC die area is rapidly increased to 30-40% as the digital side over-scales in attempt to keep costs in line with Moore’s law. New 3D IC stacking technology concepts being introduced, which need to maintain the over-scaling and keeping the overall cost scaling on Moore’s Law historical trend line. Cost scaling can be enhanced with advanced methods on direct wafer boding, 3D-TSV or inductive coupling, which will come at a total power tradeoff, as the total combined die area will increase compared to a monolithic die. Continues innovation in area over-scaling and derivative technology approaches such as FDSOI will keep the current SoC’s scaling near the historic Moore’s Law trend to serve appropriate applications optimized in performance, power, and cost.

Fatigue life prediction of Package-on-Package stacking assembly under random vibration loading

This paper presents a general methodology to predict the fatigue life of the Package-on-Package (PoP) under random vibration loading by means of vibration tests and finite element (FE) simulation. The behavior of the critical solder joints of the PoP under vibration loading was accurately described by FE model using ANSYS software and confirmed by modal analysis and linear sweep tests. The stress-life (S-N) curve of the PoP solder joints was obtained by the sinusoidal fatigue vibration tests and FE simulations to characterize the fatigue properties of the PoP under vibration. The comparison of the S-N curves of the SAC305 solder joints in different structures indicates the S-N curve of the SAC305 solder joints depends on the package structure. With the same fatigue cycles, the stress levels for the current 3D package is the smallest compared with the other 2D package due to the stacked structure of the PoP. Spectrum analysis for the random vibration tests was performed by the FE simulations to acquire the stress response power spectral density (PSD) of the critical solder joint. A specific frequency domain approach based on the Palmgren-Miner's rule was established to predict the fatigue life of the PoP under random vibration. Results show that simulated fatigue life matches well with the random vibration test results, which implies that this approach could be a potential method for the predication of fatigue life of the 3D packaging under random vibration.

A non-axial superconducting magnet design for optimized patient access and minimal SAD for use in a Linac-MR hybrid: proof of concept

A prototype rotating hybrid magnetic resonance imaging system and linac has been developed to allow for simultaneous imaging and radiation delivery parallel to B0. However, the design of a compact magnet capable of rotation in a small vault with sufficient patient access and a typical clinical source-to-axis distance (SAD) is challenging. This work presents a novel superconducting magnet design as a proof of concept that allows for a reduced SAD and ample patient access by moving the superconducting coils to the side of the yoke. The yoke and pole-plate structures are shaped to direct the magnetic flux appropriately. The outer surface of the pole plate is optimized subject to the minimization of a cost function, which evaluates the uniformity of the magnetic field over an ellipsoid. The magnetic field calculations required in this work are performed with the 3D finite element method software package Opera-3D. Each tentative design strategy is virtually modeled in this software package, which is externally controlled by MATLAB, with its key geometries defined as variables. The optimization variables are the thickness of the pole plate at control points distributed over the pole plate surface. A novel design concept as a superconducting non-axial magnet is introduced, which could create a large uniform B0 magnetic field with fewer geometric restriction. This non-axial 0.5 T superconducting magnet has a moderately reduced SAD of 123 cm and a vertical patient opening of 68 cm. This work is presented as a proof of principle to investigate the feasibility of a non-axial magnet with the coils located around the yoke, and the results encourage future design optimizations to maximize the benefits of this non-axial design.

High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

This paper presents a vision for the future of 3D packaging and integration of silicon carbide (SiC) power modules. Several major achievements and novel architectures in SiC modules from the past and present have been highlighted. Having considered these advancements, the major technology barriers preventing SiC power devices from performing to their fullest ability were identified. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were described, and the concept for a novel SiC power module was discussed.

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

3D including 3DIC and 3D Packaging (PoP)

3D including 3DIC and 3D Packaging (PoP)

Formation of highly preferred orientation of β-Sn grains in solidified Cu/SnAgCu/Cu micro interconnects under temperature gradient effect

β-Sn grain orientation and configuration are becoming crucial factors to dominate the lifetime of solder interconnects in three-dimensional integrated circuit packaging. In this paper, we found that a temperature gradient during solidification significantly dominated the orientation and configuration of the final β-Sn grains in Cu/SnAgCu/Cu micro interconnects. Being different from the random orientations and growth fronts meeting or cyclic twin boundary forming near the center after homogeneous temperature bonding, the β-Sn grains solidified under a certain temperature gradient were observed to follow a highly preferred orientation with their c-axis departing from the direction of temperature gradient by about 45°–88°. Meanwhile, these preferred oriented β-Sn grains consisted of low angle grain boundary structures with misorientation in the range of 0°–15°. The mechanism was explained in terms of the anisotropy and directional growth of β-Sn grains. The results pave the way for grain orientation control in 3D packaging technology.

The carbon wire bundle’s constructing as a capillary wick in the flat thin heat pipe

Flat plate heat pipe is required to be thin to apply 3D electronic package, which leads to declining heat transfer rate. Many studies enhance thermal performance by using various groove shapes, screen mesh, and mixed structures as wick. Nevertheless, these studies have not generated remarkable results. In the present study, we utilized carbon wire wick structure to improve the heat transfer rate of flat thin heat pipe (FTHP). The fabricated flat heat pipe in this study uses an aluminum container with 2mm thickness and 12 channels to width direction via extrusion. The cross section of the aluminum container is designed as a groove wick structure at one side of the channel; a carbon wire is inserted to the other side. The carbon wire diameter is 7µm, and the sharp edges made by carbon wires can contribute to capillary force creation. The 1 k carbon wire consists of a thousand carbon filaments. If the FTHP with carbon wire wick is developed, a valuable thermal solution with light weight, high thermal performance, thin thickness, and large contact area can be offered for electronic and telecommunication thermal management field. We developed a process for carbon wire attachment to the aluminum container. We bent both ends of an aluminum container, attached a carbon wire to the aluminum container, and cut an aluminum container. The carbon wire goes through the vacuum and seals the aluminum container. We fabricated FTHP with four kinds of carbon wires (3k, 5k, 7k, and 10k) to evaluate heat pipe performance. Result showed that the 5k carbon wire wick heat pipe showed the highest isothermal performance. The 5k carbon wire wick heat pipe recorded a lower temperature difference between evaporator and condenser of about 8.7%, 55.6%, and 3 times contrast the 3k, 7k, and 10k carbon wire wick heat pipe. The carbon wire wick FTHP showed a lower thermal resistance and higher heat transfer than the groove wick FTHP.

Low Thermal Expansion Coefficient Electrodeposited Copper and Its Contraction Mechanism by Annealing

Through-silicon via (TSV) filling by copper electrodeposition is the key technology used in 3D packaging. The thermal expansion coefficient (TEC) mismatch between the copper and silicon causes TSV pumping. Electrodeposited copper with a low TEC additive starts to contract at 120°C. The difference in expansion length between conventional copper and electrodeposited copper with the low TEC additive increases with annealing. This difference is about 47 μm at 400°C. The dark spots that exist in the in-situ SEM annealing stage at 310°C and their number increase with the increasing annealing temperature. Based on an FE-AES analysis, several 100-nm dark spots are carbon precipitates. From the X-ray diffraction, the lattice constant contracts by annealing at 420°C for 1 hour. The as-deposited copper has carbon inclusions in its lattice. This carbon diffuses out at high temperature, hence the lattice contract. This non-equilibrium to equilibrium transformation by annealing causes copper contraction during the annealing.

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

Silicon Wafer Integrated Fan-out Technology

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Through Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT methodology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single and multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer-level packaging technique. The fine feature capabilities can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enable the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products. SWIFT is a trademark of Amkor Technology, Inc.

Technology Review of System in Package

The Moore's law is approaching to an end at today's 14 nm technology and System in Package (SiP) is a promising solution for achieving denser electronics like mobile phones with small form factors. System in package is bringing together multiple ICs of various functionality stacked in 3D fashion. A fully functional system consisting of passive elements like resistor, capacitor, inductors, electromechanical elements, antenna, and ICs like sensors, can be integrated into a single package. To meet the requirements of the end product, system design characterization becomes very important for overall success in the development of system in package. Failure analysis and testing of the end product helps improve the product yield which is a point of concern for industries while designing system in package. But system in package has proven to be a viable solution for reduction in total cost and minimize time-to-market. Hence, system in package will continue to thrive and grow into mainstream technology despite of challenges faced during the development and production phase. In this paper, summary of system in package is presented with the perspective of reviewing the research carried out to overcome the challenges, cost issues, compatibility of different functional dice, quality and reliability issues. This paper discusses the recent technological development of system in package modules and the limitations faced at various system levels while bringing multiple chips together to achieve fully functional package. This paper focuses on bridging the gap between the system integration by reviewing the research progress in the 3D IC and packaging using system in package. Some of the applications like portable electronics, automotive and wearable electronics, where the significance of system in package is more relevant are reviewed in this paper. The core challenges like thermal management, flip chip or wire bond interconnect that arise due to integration of different components and packages like package on package, package in package in the system in package are also discussed.

3D Modular Power Electronic Packages and Modules for different power classes - from 50W to 50kW

This paper will describe the use of embedded die technologies for various application fields. The main focus of the paper will be the development work within the European funded project EmPower, which concentrates on power electronic applications. Here, three different power levels are of interest:50W single die packages with fast rectifier diodes500W power modules for electric bicycle application50kW power modules for HEV and EV application All three application fields are based on a similar concept. The so called power core provides the base for the package/module. This power core contains the embedded semiconductor(s) and is manufactured using printed circuit board processing on a large panel format of 18 by 24 inches. Electrical contacts to the embedded dies are made by laser drilled micro vias and copper filling. A major advantage of such a direct copper contact, compared to the conventionally used wire bond, is its high reliability and the improved electrical performance. By the reduction of the inductance of these interconnects, switching losses can be reduced significantly, allowing an improved and faster switching. For the higher power modules additionally thermal management is required. Here a construction of IMS substrates and the power core is chosen. This construction enables a double sided cooling and also the electrical isolation of the module to the cooler. The connection between power core and IMS substrates is made by low temperature and low pressure Ag sintering. All three applications fields will be described in detail. This will cover the development of the manufacturing process for all three power class demonstrators, as well as detailed structural analysis and reliability testing. The development work toward highly reliable modules will be discussed in depth. Finally the resulting demonstrators for 50W, 500W and 50kW power application and their characteristics will be presented in detail.