3D Packaging Research Articles

Two New Ways of Documenting Miniature Incisions Using a Combination of Image-Based Modelling and Reflectance Transformation Imaging

Digital 3D documentation methods such as Image-Based Modelling (IBM) and laser scanning have become increasingly popular for the recording of entire archaeological sites and landscapes, excavations and single finds during the last decade. However, they have not been applied in any significant degree to miniature incisions such as graffiti. In the same period, Reflectance Transformation Imaging (RTI) has become one of the most popular methods used to record and visualize this kind of heritage, though it lacks the benefits of 3D documentation. The aim of this paper is to introduce two new ways of combining IBM and RTI, and to assess these different techniques in relation to factors such as usability, time-efficiency, cost-efficiency and accuracy. A secondary aim is to examine the influence of two different 3D processing software packages on these factors: The widely used MetaShape (MS) and a more expensive option, RealityCapture (RC). The article shows that there is currently no recording technique that is optimal regarding all four aforementioned factors, and the way to record and produce results must be chosen based on a prioritization of these. However, we argue that the techniques combining RTI and IBM might be the overall best ways to record miniature incisions. One of these combinations is time-efficient and relatively cost-efficient, and the results have high usability even though the 3D models generated have low accuracy. The other combination has low time- and cost-efficiency but generates the most detailed 3D models of the techniques tested. In addition to cost-efficiency, the main difference between the 3D software packages tested is that RC is much faster than MS. The accuracy assessment remains inconclusive; while RC generally produces more detailed 3D models than MS, there are also areas of these models where RC creates more noise than MS.

Anisotropic Copper Electrodeposition on Microelectrodes

Copper electrodeposition is critical to electronics manufacturing, ranging across lengthscales from nanometer damascene plating to 100s of micrometers for through-silicon-vias in 3D interconnect packaging and even millimeter-scale in printed circuit board manufacturing. Essential to this process is formation of void-free copper structures in high aspect ratio cavities, which is achieved with various additives that enable superconformal or bottom-up electrodeposition. When the additive package consists of only a suppressor (polyether) and chloride, the superconformal phenomenon is driven by S-shaped negative-differential resistance (S-NDR), which promotes spatial bifurcation of the electrode surface into active and passive depositing regions. All S-NDR systems involve kinetic suppression, polyether-chloride adsorption in this case, and kinetic activation, potential-driven disruption of the polyether-chloride adlayer. The term S-NDR is derived from the s-shape the i-V curve expresses when cyclic voltammetry (CV) is post-experimentally corrected for ohmic resistance, resulting in a system that expresses a multiplicity of reaction rates (current) for a given driving force (potential).Electroanalytical measurements using microelectrodes (UMEs) offer an avenue for exploring S-NDR systems without significant iR-drop in solution. In other reaction systems, the reduced electrode dimension of UMEs has shown the ability to frustrate active-passive bifurcation, resulting in a homogeneously reacting electrode surface. Nonetheless, potential-controlled measurements such as cyclic voltammetry restrict S-NDR behavior from fully expressing itself, as the potential is the control parameter throughout the experiment. Current-controlled techniques, however, allow the thermodynamic state (i.e., potential) to dynamically shift as the polyether-chloride suppressing layer is formed and disrupted. In this work, current-controlled measurements in the form of linear galvanodynamic sweeps (GDS) are utilized to explore S-NDR behavior and electrode bifurcation during copper electrodeposition. GDS and CV measurements on UMEs are compared across a range of additive concentrations and polyether types. Influence of the operating mode on pattern formation is evaluated by in-situ optical microscopy on UMEs ranging from 10 μm to 25 μm in diameter. Spatial bifurcation during GDS measurements is further exploited to grow anisotropic copper deposits.

A boundary element procedure to analyze the thermomechanical contact problem in 3D microelectronic packaging

The interface between two surfaces in contact is formed by numerous microcontacts and gaps separating both surfaces. The heat flow from one surface to the other has to overcome these gaps by means of a thermal contact resistance. In microelectronic packaging it is necessary to evacuate the heat from the microprocessor, so it is important to have a great conductance of the heat flow between the microprocessor and the heatsink. This work studies the 3D microchip-heatsink contact in microelectronic packaging using the boundary element method. The formulation includes a variable thermal contact resistance along the contact zone formed in the interfase between the microchip and the heatsink. The thermal contact resistance is a function of the contact normal traction, so the thermal and the thermoelastic problems are coupled. The values of the final thermal and mechanical variables of the boundary of the microelectronic packaging and the thermal contact resistance are obtained by a double iterative schema.

Analysis and control of Cu6Sn5 preferred nucleation on single crystal (0 0 1)Cu

Fully oriented-intermetallic interconnects (FOI) of high melting point and service performance have highly considerable potential application in the current generation of 3D electronic packaging. The primary process of fabrication of this structure is the Cu6Sn5 preferred nucleation. In this article, the orientations of 59 successive Cu6Sn5 grains along the radius of (0 0 1)Cu/Sn-3.0Ag solder interface were investigated. Finally, an analysis and control model of Cu6Sn5 preferred nucleation determined by chemical potential gradient of Cu migration was established and applied to address and manage the orientation growth of Cu6Sn5 under different reflow temperatures and solder compositions. The results pave the way for orientation controlling of interfacial intermetallics in 3D packaging technologies.

Inhibition of intermetallic compounds growth at Sn–58Bi/Cu interface bearing CuZnAl memory particles (2–6 μm)

In total, 0.5 wt% CuZnAl memory particles with the diameters (2–6 μm) were added into Sn–58Bi solder in order to enhance the properties of solder joints in electronic packaging. The interface reaction and the growth kinetics of intermetallic compounds at Sn–58Bi/Cu interface and Sn–58Bi–0.5CuZnAl/Cu interface were studied systematically at 250 °C, 230 °C and 210 °C, the results indicate that the growth rate of intermetallic compounds (IMC) at both interfaces at 250 °C was higher than that at 230 °C, the addition of CuZnAl memory particles can reduce the diffusion coefficient of interfacial IMC, and however, at 210 °C the inhibition effect of CuZnAl particles was so small. Based on the transient liquid phase bonding, it is demonstrated that Cu/Sn–58Bi–0.5CuZnAl/Cu-bonded joints can achieve the chip stacking in 3D packaging with 10 μm thickness with obvious superiority.

Study on Physical Properties of Ultrasonic-Assisted Copper Electrodeposition in Through Silicon Via

Through silicon via (TSV) connection plays a significant role in 3D packaging technology. In this paper, copper electroplating in TSVs under different ultrasonic powers was realized through an ultrasonic electroplating system. The physical properties (surface roughness, Young’s modulus and hardness) of ultrasonic-assisted copper electrodeposition in TSV were analyzed. Copper grain size inside the via was also measured and compared. Based on the analysis of experimental results, a conclusion could be reached that the increase of ultrasonic power has an effect on the physical properties of copper plating in TSV. It can effectively reduce the surface roughness of the copper plating surface. Besides, the increase of ultrasonic power can increase the values of Young’s modulus and hardness. It is also found that the decrease in copper grain size results in a tight connection between copper crystal grains. Explanations on the changes of physical properties under different ultrasonic power have been provided.

Effects of Cooling Rate and Joint Size on Sn Grain Features in Cu/Sn-3.5ag/Cu Solder Joints

In Sn-based micro solder joint s for fine pitch flip chip or 3D packaging technologies , the number of Sn grains is always limited and sometimes only one Sn grain exists in a joint, which inevitably causes anisotropy in the performance of micro interconnection. It is known that the parameters and reliability of solder joint structure and reflow process, especially cooling stage, have a great significance for regulating the features of Sn grain s after soldering. Hence, in the present paper, the Sn grain features of Cu/Sn-3.5Ag/Cu solder joints with different joint size s (300 μm, 100 μm and 50 μm) solidified under different cooling rate s (1.5 °C /s, 0.5 °C /s and 0.1 °C /s) were studied. Generally, the number of Sn grains decrease d as the joint size decrease d . When the joint size was 50 μm, the solder joints tended to contain only one or two Sn grains irrespective of the cooling rate. Furthermore, cooling rates greatly affected the number and orientation of Sn grains as well as the growth of large Ag3Sn intermetallic plates to varying degrees. The formation of Sn grains and Ag 3 Sn plates was discussed from the viewpoint of nucleation under different conditions.

Numerical and experimental analysis of high-aspect-ratio micro-tool electrode fabrication using controlled electrochemical machining

Numerical and experimental analysis of high-aspect-ratio micro-tool electrodes fabrication using a controlled electrochemical machining (ECM) technique is reported. The evolution of the tool electrode shape was first predicted using a finite element method-based numerical simulation and then validated with the detailed experiments. The effects of machining voltages and the machining durations on the change in the tool electrode profile were investigated. High-carbon steel was chosen as an electrode material due to its lower cost, good electrical conductivity, and easy availability. A 5% (i.e., 5 gm of NaCl in 100 ml of deionized water) NaCl solution was used as the electrolyte. The tool profiles predicted using the FEM-based numerical model showed an excellent matching trend with the ECM experimental results. The role of the black surface film formed on the electrode surface was found to be significant. The tool electrodes having an average diameter of 60 µm and an aspect ratio of more than 75 were fabricated at the optimized machining parameters. These single-tip micro-tool electrodes were used to create through-hole in a 400-µm-thick glass substrate by electrochemical discharge machining. The obtained ECM process parameters were used to create multiple electrodes having a tip size of 130 µm and having a smooth surface. These through-holes were filled with copper to form 3D interconnects, i.e., through-glass vias, which are required in the radio-frequency MEMS applications and 3D packaging.

Damage Mechanism of Cu6Sn5 Intermetallics Due to Cyclic Polymorphic Transitions.

The formation of high-melting-point Cu6Sn5 interconnections is crucial to overcome the collapse of Sn-based micro-bumps and to produce reliable intermetallic interconnections in three-dimensional (3D) packages. However, because of multiple reflows in 3D package manufacturing, Cu6Sn5 interconnections will experience cyclic polymorphic transitions in the solid state. The repeated and abrupt changes in the Cu6Sn5 lattice due to the cyclic polymorphic transitions can cause extreme strain oscillations, producing damage at the surface and in the interior of the Cu6Sn5 matrix. Moreover, because of the polymorphic transition-induced grain splitting and superstructure phase formation, the reliability of Cu6Sn5 interconnections will thus face great challenges in 3D packages. In addition, the Cu6Sn5 polymorphic transition is structure-dependent, and the η′↔η polymorphic transition will occur at the surface while the η′↔ηs↔η polymorphic transition will occur in the deep matrix. This study can provide in-depth understanding of the structural evolution and damage mechanism of Cu6Sn5 interconnections in real 3D package manufacturing.

Evaluation of Three-Point Bending Strength of Thin Silicon Die With a Consideration of Geometric Nonlinearity

With the trends of electronic packaging development toward small size, low-profile features, high-pin count, and high performance, the 3D IC (Three-dimensional Integrated Circuits) or stacked-die packages have been gaining popularity. For such package applications, IC silicon wafers have to be ground and processed to be relatively thin and then the thin silicon dies cut from these wafers have to gain sufficient strength in order to bear high stresses resulting from process handling, reliability testing, and operations. Hence, the strength of the thin dies has to be determined to ensure the good reliability of the packages. Three-point bending test is commonly used for measuring die strength; however, the feasibility of the test is still questionable for determining the strength of relatively thin dies. Therefore, the feasibility of the linear beam theory is evaluated by a nonlinear finite element method (NFEM) with taking into account geometric nonlinearity in this study. The results show that this nonlinearity would cause errors of the strength of thin dies if calculated by the linear beam theory. The fitting equations of the correction factors ( $\eta $ ) to linear solutions, extracted from the NFEM simulation, are proposed and proved to be workable with very good accuracy. It is also found that the correction factor highly depends on the deflection ( $\delta $ ), span length (L) and radius of roller support (r), but not elastic modulus (E) and thickness (t) of test specimens. After the nonlinearity has to be taken into account for the relatively thin silicon dies, the consistent statistical strength data have been obtained for various thicknesses of the test die specimens.

Gradient growth of fcc and bcc phase within FexNi1−x (50 < x < 75) films during direct-current wafer electroplating

In order to investigate the performance of Fe-Ni magnetic cores within embedded inductor in 3D package, a series of Fe-Ni films with compositions ranging from 15 wt% to 80 wt% iron were electrodeposited on 8-inch silicon wafer. The uniformity on brightness, phase structure and grain size of Fe-Ni magnetic films were investigated through SEM (scanning electron microscopy) and XRD (X-ray diffraction). A gradient growth behavior of fcc (face-centered cubic) and bcc (body-centered cubic) phase was revealed when Fe content ranges 50–75 wt% within Fe-Ni films, which can be attributed to the slightly faster growth rate of fcc phase. As also revealed in TEM (transmission electron microscope) observation, the fcc phase gradually spread over bcc phase region during the electroplating process, and formed an interface with a slight tilt angle to the substrate on the thickness direction. Several methods, such as increasing solution stirring, temperature or decreasing the current density, were proposed to restrain the gradient growth behavior of Fe-Ni film in wafer level.

Thermal management and structural parameters optimization of MCM-BGA 3D package model

The multi-core technology promotes the efficiency improvement of microelectronic devices. However, the increasing power and heat flux lead to heat dissipation problems on hotspots, which severely affects the performance of electronic devices and impedes the development of electronic techniques. Therefore, thermal management suitable for electronic packaging is crucial. In this paper, a multi-chips module combined with ball grid array (MCM-BGA) 3D package model was established; the thermal interface resistance between the micro-channel heat sink and heat spreader was considered; the flow heat transfer as well as thermal stress performance of the model were discussed. The results indicate that the MCM-BGA 3D package model can maintain the maximum temperature and thermal stress in a satisfactory range. However, the major concentration areas of the maximum temperature are the chips and solder balls, especially the welding spots. Based on the analysis, the multi-parameters optimization of structural parameters was conducted. After the optimization, the maximum temperature and thermal stress decrease by 5 K and 20% in average, respectively. The optimal thickness of thermal interface material, heat spreader and substrate are 0.1 mm, 1.2 mm and 1.2 mm, respectively.

The BACH classification of long bone osteomyelitis.

ObjectivesThe aim of this study was to assess the clinical application of, and optimize the variables used in, the BACH classification of long-bone osteomyelitis.MethodsA total of 30 clinicians from a variety of specialities classified 20 anonymized cases of long-bone osteomyelitis using BACH. Cases were derived from patients who presented to specialist centres in the United Kingdom between October 2016 and April 2017. Accuracy and Fleiss’ kappa (Fκ) were calculated for each variable. Bone involvement (B-variable) was assessed further by nine clinicians who classified ten additional cases of long bone osteomyelitis using a 3D clinical imaging package. Thresholds for defining multidrug-resistant (MDR) isolates were optimized using results from a further analysis of 253 long bone osteomyelitis cases.ResultsThe B-variable had a classification accuracy of 77.0%, which improved to 95.7% when using a 3D clinical imaging package (p < 0.01). The A-variable demonstrated difficulty in the accuracy of classification for increasingly resistant isolates (A1 (non-resistant), 94.4%; A2 (MDR), 46.7%; A3 (extensively or pan-drug-resistant), 10.0%). Further analysis demonstrated that isolates with four or more resistant test results or less than 80% sensitive susceptibility test results had a 98.1% (95% confidence interval (CI) 96.6 to 99.6) and 98.8% (95% CI 98.1 to 100.0) correlation with MDR status, respectively. The coverage of the soft tissues (C-variable) and the host status (H-variable) both had a substantial agreement between users and a classification accuracy of 92.5% and 91.2%, respectively.ConclusionsThe BACH classification system can be applied accurately by users with a variety of clinical backgrounds. Accuracy of B-classification was improved using 3D imaging. The use of the A-variable has been optimized based on susceptibility testing results.Cite this article: A. J. Hotchen, M. Dudareva, J. Y. Ferguson, P. Sendi, M. A. McNally. The BACH classification of long bone osteomyelitis. Bone Joint Res 2019;8:459–468. DOI: 10.1302/2046-3758.810.BJR-2019-0050.R1

Reliability of printed wire bonds

Abstract Additive manufacturing is an emerging domain with numerous potential applications. The concept of those new processes offers many advantages such as design flexibility, truly 3D packages and low cost for customization. The aerosol jet printing could enable wire bonding-like techniques that are unachievable with round wires today, combined with serious advantages for high frequency applications. However, this new field is starting off with many challenges to address, with the reliability as a focal point. The focus of this study is the reliability of printed wire bonds. Polyimide and silver inks were printed using an aerosol jet system (OPTOMEC Aerosol Jet ® HD Decathlon™). The results are focusing on the reliability of the adhesion of polyimide ink (UTD-PI-AJ) in an ethanol-based diluent and a silver ink, the HPS-108AE1 from Novacentrix, on different surface types: silicon oxide, pure aluminum and gold (ENIG). The adhesion is first addressed by a qualitative tape test at room temperature. The test samples are then put into an environmental chamber for a Deep Thermal Cycling (DTC) stress. The samples cycled 1000 times between −20°C and 85°C. They were inspected for physical defects at 250, 500 and 750 cycles. The visual inspection for defects focuses on cracks and delamination. The printed wire bonds were simulated by printing polyimide ink into a gold plated flat ceramic substrate (28 LCC from Kyocera) and then printing conductive silver ink from opposite pin leads. A layer of polyimide ink was then added on top of the printed lines. Crossover lines were finally printed on top of the last polyimide layer, again from opposite pin leads, creating an array of superimposed printed wire bonds. The reliability of printed wire bonds is tested through a Highly Accelerated Stress Test (HAST, 110°C, 85%RH, 264h) under bias. The samples were inspected at 66h, 132h and 198h for visual defects such as cracks, delamination and silver electro-migration. Cross-sections were performed on samples before and after HAST. All defects were characterized regarding of their time and condition or appearance and of their dimensions.

Recent Advances in X-ray for Semicon Applications

Abstract Taking x-ray images goes back over 100 years. Since then, there have been numerous advances in x-ray technology and these have been increasingly applied in helping the manufacturing of electronic components and assemblies, as well as in their failure analysis. Most recently, this has been rapidly driven by the reduction in device and feature size and the movement to using newer, lower density materials within the structures, such as copper wire replacing gold wire as the interconnection material of choice within components. Another driver for developments is the engineering of single 3D packages with multiple chips stacked vertically one on top of the other, which results in smaller and more efficient packaging of devices. In order to meet these challenges and those in the future, there have been a number of recent key improvements to the vital components within x-ray systems. The choice of available technologies, however, means selecting the tube/detector combination, which is optimum for a particular electronics inspection application, is no longer so clear-cut. For example, one configuration may provide certain benefits that are applicable for one area of electronics inspection, whilst being less valid for others. This paper will review the various x-ray tube and detector types that are available and explain the implications of these choices for electronics inspection in terms of what they provide for inspection regarding image resolution, magnification, tube power, detector pixel size and the effects of detector radiation damage, amongst others. This paper will also look in detail at the capabilities of high end CT systems to inspect wafer bumps, copper pillars and TSV's, new designs are reducing key dimensions of all of these interconnections challenging x-ray systems to produce clear images.

Flip Chip Joining with Quaternary Low Melting Temperature Solder Bump Fabricated with Injection Molded Solder

Abstract IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.

(Invited) Trends in 3D Markets and Technology

Driven by performance, 3D packaging with through silicon vias (TSVs) has become a reality for memory and advanced logic. New versions are emerging. High Bandwidth Memory (HBM) is one of the most important 3D IC developments in the last 10 years. In the last decade, stacked DRAM with through silicon vias has transitioned from a handful of research programs to rapidly increasing volumes. Tezzaron has been providing small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015. Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a BGA and tested before assembly on the board. The HMC has been used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC. Thermal issues were a challenge. Today Samsung and SKHynix are providing HBM stacks to the industry and Micron is expected to ship products next year. In February 2018, Samsung announced that its first “three-layer” stacked CMOS image sensors (CIS) were in mass production and found in the Galaxy S9/S9+. This follows Sony’s adoption of three-layer CIS technology one year earlier in February 2017. A third silicon layer in the form of DRAM is added to the pixel array and signal processing layers to significantly improve data readout speeds. These devices are manufactured with 3D IC technologies using TSVs, but Samsung and Sony use different design approaches. Technically speaking, Samsung’s solution is a two-layer image sensor with a stacked DRAM. Sony uses a true three-layer bonded approach. In its three-layer CIS technology, Sony places the DRAM between the pixel array die and the image processor, with all three layers interconnected using TSVs. The pixel array, DRAM, and logic wafers are manufactured with 90nm, 30nm, and 40nm processes, respectively. While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration. The technology uses a 3D face-to-face stacking process. In the process, logic die are bumped and mounted on an active interposer next to memory or die with other functions. The active interposer can contain active parts of the system, such as the platform controller hub (PCH) that manages I/O for the system. The active interposer is mounted on a package substrate with solder bumps. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW). These technologies are front-end packaging and use direct or fusion bonding. The SoIC is a wafer with logic, with our without TSVs.

Estimation of through-Plastic Via (TPV) Filling through Computed Tomography for Dielectrics and Conductive Inks in Flexible Printed Electronics

Computed Tomography (CT) is an advanced optical imaging tool for non-destructive 3D analysis of test structures compared to the conventional imaging tool Scanning Electron Microscopy (SEM). SEM has been used extensively for analyzing the via filling1, however as per the available literature the CT-scanner has not been employed for via filling analysis of through plastic vias (TPV). In this study, we have employed both the techniques for investigating the via filling and calculating the fill ratios in TPV. A non-destructive 3D imaging technique is essential for estimating the fill ratio while overcoming the loss of material that can be accrued in sectioning samples for SEM. We show that CT-Scanning achieves a better estimation of via-filling. This method can be useful for PCB/circuit designers in obtaining a higher accuracy of via-resistance (for conductive inks) and a better 3D packaging reliability (for dielectric polymers2). This technique also shows an additional advantage for scanning dielectric materials as it doesn’t require pre-processing step of metal deposition. Images from CT-Scanning and SEM have been presented in Fig. 1 (a) and (b) respectively. Vias in different samples were prepared by laser ablation using a pico-second Nd:YAG laser3. Via-filling was accomplished by screen-printing on both sides of polyethylene terephthalate (PET) using a 325 stainless-steel mesh screen and CI-1036 (silver ink) 4,5 individually and separately with DI-7540 (dielectric). Curing of all the printed inks were done at 1220C for 12 minutes individually. No treatment of the substrates was carried out before printing. A 7-mil (177 µm) thick PET with a surface energy of 28.3 mN/m was used as a substrate for this study. Samples were first freeze-dried and cut before being used for SEM whereas samples used for CT-scanning did not require any pre-processing. Three samples for each diameter were investigated through SEM and CT-Scanning. Fill ratios from SEM images was quantified using the method outlined in other studies for through silicon vias (TSV)6,7 (Fig. 1(c)). Two sections (the center and bottom of the via) of the scanned samples were inspected for measuring the thickness of deposited material that is filled in the walls of via, as illustrated in Fig. 1 (d). For the CT-scanned images the process for calculating the fill ratio was as follows. First, the image processing toolbox of MATLAB was used to mark different points on the curvature (Fig. 1(c)) and then these points were converted into cartesian coordinates. These coordinates were then fitted into a quadratic equation of second degree to obtain an equation in f(x) (where x is parallel to cross section of the via). The volume of the cured silver was then calculated by using Eq. 1 and the fill ratio was calculated using Eq. 2. Vfill= Π∫(f(x))2 dx (1) Fill ratio=Vfill/Πr2l (2) where r is the radius of the via and l is the length of the via. The fill ratios of different diameter vias are presented in Fig. 1 (e) (only CI-1036) & Fig. 1(f) (CI-1036 and DI-7540). A mean difference of 21.11% for CI-1036 and 16.44% for DI-7540 in fill ratios was observed between CT and SEM. The work aims to address the uncertainty that may occur due to sample pre-processing required for SEM. It also discusses a rigorous approach for estimation of the via fill ratio of liquid phase materials such as dielectric or conductive inks in TPVs. *Acknowledgement This work was supported in part by the National Science Foundation (IIP-1439644) through the Multi-Functional Integrated Systems Technology (MIST).

Two-Step Plasma Treatment on Sputtered and Electroplated Cu Surfaces for Cu-To-Cu Bonding Application

The technology trends of next generation electronic packaging are moving toward heterogeneous 3D packaging systems. One of the key processes of 3D packaging system is Cu-to-Cu bonding, which is highly dependent on the planarized, activated, and oxygen-free Cu surface. A two-step plasma treatment is studied to form a Cu surface that does not react with oxygen and improves the Cu bonding interface quality at low bonding temperature (300 °C). In this study, the effects of two-step plasma treatment on both sputtered and electroplated Cu surfaces were evaluated through structural, chemical, and electrical analysis. The Cu bonding interface was studied by scanning acoustic tomography analysis after the thermocompression bonding process. Both sputtered and electroplated Cu thin films had the preferred orientation of (111) plane, but sputtered Cu exhibited larger grains than the electroplated Cu. As a result, the roughness of sputtered Cu was lower, and the resistivity was higher than that of electroplated Cu. Based on X-ray photoelectron spectroscopy analysis, the sputtered Cu formed more copper nitrides and fewer copper oxides than the electroplated Cu. A significant improvement in bonding quality at the Cu bonded interface was observed in sputtered Cu.

The Auto-focus Method for Scanning Acoustic Microscopy by Sparse Representation

As an efficient non-destructive checking technique, scanning acoustic microscopy has been rapidly developed and widely used in nondestructive detection for composites, chip manufacturing, bio-pharmaceuticals and so on. Scanning acoustic microscopy can obtain the two-dimensional image and reconstruct three-dimensional model of the internal structure inside the sample, compared with the optical microscope. Due to the geometrical features of high frequency transducer, the precision of focus has already become the key factor for the digital imaging and defect detecting. Especially for the current 3D packaging chips and multi-layer composite materials, thickness of layer has reached the level of nm. Different focus plane will provide a completely different digital image. However, the process of focusing has been relying on manual operation without great development until now. To improve the speed and accuracy of the focusing, we proposed a quick auto-focus method on scanning acoustic microscopy. This method can be divided into three steps. The first one is fast auto-focusing on upper surface, the second other one is auto-focusing on the interlayer base on V(z) curve, and the last one is to improve the A-Scan signal of points in the V(z) curve with spars signal representation. This method is integrated into Scanning Acoustic Microscopy imaging software and has been validated in the experiment with Olympus transducers at 30\\50 MHz. It can be seen that this method can effectively improve the accuracy of focus and shorten the focus time of Scanning Acoustic Microscopy through experiments.