A major form of 3D integration is incorporating memory die in the package along with the processor die. Higher-end applications incorporate DRAMs within the package in 3D or 2.5D configurations, to provide extremely high bandwidth and relatively large capacity. The added component cost and assembly and test process cost demand step-function yield improvement. This talk will focus on recent developments in DRAM System-In-Package (SiP) integration, outlining assembly process induced failure modes and risk mitigations. These DRAM products, including “High-Bandwidth Memories” (HBM) in “known good stacked die package form,” must be economically testable and efficiently debuggable, yet the interface between the SOC die and the DRAM is usually a buried interface. Testability and alignment with the back-end assembly and test processes are crucial planning activities for such products.