3D IC Packaging Technology Research Articles

A novel heat transfer characterization method for a thermal management scheme of 3D-IC chips

A novel surface-modified silicon-based thermal management technology has been proposed for 3D IC architecture in this study. 2 × 2 cm2 double sides polished silicon chips’ surface with micro-fin (MF) and micro-pin fin (MPF) structures have been achieved by applying silicon microfabrication technology of deep reactive ion etching, which is applicable to the interlayer of 3D IC packaging technology. By integrating a mini wind tunnel with Raman spectrometer, the transient thermal property measurement system is originally designed to evaluate the cooling capability of the surface-modified silicon interlayer. Finite Element Analysis was involved to confirm this view by taking fluid dynamics and heat transfer into account. The sample with 100 × 100 µm2 MPF structure expresses the appropriate exponential decay time constant τ (with unit of 1), which is 4.71 and 8.53 under cooling and heating measurement conditions, respectively. This also proved that the combination of Raman thermometry with forced gas flow could be a relevant measurement tool for transient thermal property.

In situ study on interfacial reactions of Cu/Sn–9Zn/Cu solder joints under temperature gradient

Synchrotron radiation real-time imaging technology was used to in situ study the interfacial reactions of Cu/Sn–9Zn/Cu solder joints during reflow under a temperature gradient. It was clarified that both Zn and Cu atoms were driven to migrate towards the cold end by the temperature gradient, which enhanced the intermetallic compounds (IMCs) growth locally and the Cu consumption at the hot end. A Cu5Zn8 layer adhered to the hot end interface could drastically restrict the consumption of the neighboring Cu substrate till it spalled from the interface. Additionally, the crystallization of β-Sn grains was observed to follow a highly preferred orientation with the c-axis of β-Sn grains departing from the direction of temperature gradient by about 30°–40°. These peculiar phenomena may inspire future exploration of interfacial reaction and grain orientation control by temperature gradient in 3D IC packaging technology.

A study of through package vias in a glass interposer for multifunctional and miniaturized systems

Glass interposer with through package vias is a promising 3D-IC packaging technology that is expected to be used widely in the near future thanks to its numerous benefits. This technique is still being developed in research laboratories because of its low yield compared to the Through Silicon Vias which is produced on an industrial scale. In this paper, we report on our progress regarding the fabrication of the glass interposer with 3D vertical interconnects. The work consists of first fabricating samples using different techniques, then identifying the failures and defects that have effects on the interposer reliability and functionality, and finally reviewing the fabrication process to eliminate or reduce these weaknesses. The physical and electrical differences between the samples fabricated with old and new processes are discussed.

Effects of Creep Parameters of Lead-Free Solders on Fatigue Reliability of 3D IC Packages with through Silicon Vias

3D IC packaging technologies are emerging as they are able to respond to the demands for smaller form-factor, faster, high density interconnection at cheaper cost. Moreover, for a 3D IC package, through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to the nonlinear behavior of SAC lead-free solder used in the package as an echo of environmental concerns and RoHS directive. However, there exists a wide range of values of the parameters of the creep model used to describe the nonlinear behavior of SAC. The effects of the variations of these parameters on the thermal reliability of IC packages, particularly the 3D IC package with built-in TSVs considered herein, is of interest. Presented in the paper is a study on assessment of the influence of the creep parameters of SAC solders on the isothermal fatigue reliability of a 3D IC package with built-in TSVs. The results show that as the strain rate is linear proportional to C1, a larger C1 tends to enlarge the strain rate hence decrease the fatigue life. However, the relationship between the fatigue life of the specific IC package is not linear. Although the variation of C2 causes a large variation in the fatigue life, its effect becomes insignificant when a moderate value of C2 is considered. As a power parameter to the hyperbolic sine function of the creep model, C3 contributes a 40% variation to the fatigue life. Lastly, the fatigue life increases with C4 value, and the gain of fatigue life increases as C4 approaches the upper limit considered herein.

Metallurgical challenges in microelectronic 3D IC packaging technology for future consumer electronic products

Metallurgical challenges in controlling the microstructural stability of Cu and solder microbumps in 3D IC packaging technology are discussed. Using uni-directional 〈111〉 oriented nanotwinned Cu, the controlled growth of oriented Cu66n5 on the nanotwinned Cu and its transformation to Cu3Sn without Kirkendall voids have been achieved. In order to join a stack of Si chips into a 3D device, multiple reflows of solder microbumps may be required; we consider localized heating to do so by the use of self-sustained explosive reaction in multi-layered Al/Ni thin films of nano thickness. It avoids re-melting of those solder joints which have been formed already in the 3D stacking structure.

Reliability challenges in 3D IC packaging technology

At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the packaging. If we assume just a difference of 1 °C across a micro-bump of 10 μm in diameter, the temperature gradient is 1000 °C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what we have known from flip chip technology.