Abstract
Glass interposer with through package vias is a promising 3D-IC packaging technology that is expected to be used widely in the near future thanks to its numerous benefits. This technique is still being developed in research laboratories because of its low yield compared to the Through Silicon Vias which is produced on an industrial scale. In this paper, we report on our progress regarding the fabrication of the glass interposer with 3D vertical interconnects. The work consists of first fabricating samples using different techniques, then identifying the failures and defects that have effects on the interposer reliability and functionality, and finally reviewing the fabrication process to eliminate or reduce these weaknesses. The physical and electrical differences between the samples fabricated with old and new processes are discussed.
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