Interconnect design tradeoffs for silicon and glass interposers

Abstract

Interposer technologies offer high density, high performance interconnects for integrated systems resulting in smaller form factors and improved system performance as compared to traditional packages. This paper sheds light on the different design tradeoffs which result from the usage of silicon and glass interposers due to the different material characteristics. The emphasis is on the redistribution layers (RDLs) of the interposer rather than the through silicon vias (TSVs) due to the long length of these wires. Guidelines of designing the interconnects for different design objectives on silicon and glass interposers are presented. Interconnects on glass interposers are more efficient in terms of power dissipation and delay. Conversely, wires on glass interposers suffer from twice as high crosstalk as compared to silicon at minimum pitch. Interconnects on glass interposers exhibit 35% better power-delay product (PDP) than on silicon for fixed pitch at 1.95 μm. More importantly, minimum pitch does not result in minimum delay, power dissipation, and crosstalk. The interconnect design parameters that satisfy these objectives under different constraints are different for the two materials. Consequently, the various tradeoffs between area and noise as well as power and delay must be considered in the design process.