Advances in Panel Scalable Planarization and High Throughput Differential Seed Layer Etching Processes for Multilayer RDL at 20 Micron I/O Pitch for 2.5D Glass Interposers

Abstract

This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 µm lines and spaces with 4-5 µm diameter photo-vias for multiple re-distribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth need with lowest power consumption has enabled the application of 2.5D interposers for high density chip-to-chip interconnections. Silicon interposers with through-silicon-vias (TSVs) are capable of ultra-high density wiring between logic and memory chips, but use back end of line (BEOL) dual damascene processes, requiring chemical mechanical polishing (CMP), leading to high process cost, which limits their expansion into lower cost and higher volume applications. On the other hand, organic substrates processed on large panels have large capture pads for via landing due to their poor dimensional stability, limiting the bump pitch scaling at chip level. Glass interposers have been proposed to address the limitations of both silicon interposers and organic substrates in recent years. This paper reports on research to extend low cost and large panel semi-additive processes (SAP) to below 5um lines and vias. To achieve this, high resolution lithography processes combined with photosensitive dry film polymer dielectrics were optimized to form fine patterns and ultra-small micro-vias. A major challenge for multilayer RDL is the non co-planarity of copper electroplating, and a new cost-effective copper surface planarization process was proposed and evaluated for surface co-planarity improvement, leading to better yields for multi-layer RDL fabrication.