Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers

Abstract

Interposer technology is becoming important to interconnect ultra-high performance ICs with ultra-high density I/Os. Silicon interposers fabricated by back-end of line (BEOL) wafer processes address these wiring density requirements, but are limited by their high cost and by their high electrical losses. Organic interposers have limitations too. Their limitations are due to their poor dimensional stability, which require larger capture pads, which limit the I/O density Glass has been proposed by Georgia Tech [1-4] as a superior interposer material to address the limitations of both silicon and organic interposers in recent years. This paper describes the first demonstration of low cost and double sided glass interposer with 3–5 μm line lithography to form multilayer redistribution layers (RDL) to achieve 20 micron bump pitch, ready for chip-level copper interconnections. Unlike prior work using wafer based RDL processes or thin film wiring applied to organic cores, this research applies low cost laminate-like processes, scalable to large panels for lowest cost. To achieve this, semi-additive plating (SAP) process, combined with high resolution dry film photoresists, was optimized to fabricate fine-pitch copper traces with 3–5 μm lines on thin polymer films, laminated on thin glass. Such an ultra-high I/O density of interconnections form the backbone of 2.5D interposers, interconnecting multiple chips. Such ultra-small pitch copper traces can reduce the number of wiring layers required, thus reducing the cost. Compared to sub-micron Cu traces on Si interposers, these 3–5 μm lines are lower in resistance.