32-bit RISC Processor Research Articles

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Design and Implementation of High Speed and Area Optimized Vedic Processor for Embedded Systems

The proposed work on the design and implementation of a High-Speed and Area-Optimized Vedic Processor for Embedded Systems appears promising. Here's an outline that we might find useful for organizing our work. Discuss briefly the growing need for high-performance embedded systems and the crucial role of processors. Summarize prior research on Vedic Processors, highlighting major features and optimizations gained by earlier researchers. The exact Vedic mathematics ideas and sutras that we propose to exploit in our processor design. Detail tactics for obtaining high-speed operations in the CPU, taking into account parallelism, pipelining, and other optimization approaches. As the computational complexity of tiny battery-powered devices develops, this study addresses the need for a fast 16-bit RISC processor. The emphasis is on boosting processor capabilities by integrating a Multiply-Accumulator (MAC) unit based on Vedic mathematics. The inclusion of a new instruction set involves VHDL-based changes to the processor's architecture, to ensure simplicity and total compatibility with the current structure. This study describes an innovative strategy for enhancing the capabilities of modest 16-bit RISC processors by including a Vedic mathematics-based Multiply-Accumulator (MAC) unit. The objective is to improve processor functionality by providing a new instruction set, which will be performed through VHDL-based changes to the CPU's design. The newly designed instruction set keeps its structure basic, ensuring complete compatibility with the previous architecture. A 16-bit pipelined system based on Harvard design has several components in its pipeline, comprising register access, arithmetic execution, front-end logic execution, instruction fetch, and decode. The simulation results demonstrate the validity of the proposed design, demonstrating effective verification and synthesis of the MAC architecture on an FPGA platform.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

Design and Verification of LC3 Microcontroller

Abstract: The main focus of the work is on utilising System Verilog to verify and debug the LC-3 Microcontroller, a 16-bit RISC processor. The utilised LC-3 Design Under Test (DUT) contains numerous flaws in the Fetch, Decode, Execute, and Controller sub-design units as well as flaws throughout. Numerous intricate SV features, including OOPS, Randomization, Functional Coverage, Assertions, and UVM, are used to identify the problems. For testing and determining the origin of design problems, the System Verilog Hardware Verification Language is combined with the Mentor Graphics Questa Simulation Environment. As long as it adheres to the design standards, the LC-3 microcontroller used for verification is presumed to function flawlessly. Otherwise, any behaviour that is not in line with the design specifications is considered a bug. The paper offers an effective approach for Verification Engineers in the Embedded Systems Industry to use System Verilog, the newest trend in the EDA Industry today, as their preferred language for debugging.

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region

A method for runtime energy optimization based on the supply voltage (Vdd) and the threshold voltage (Vth) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

RETRACTED: Design of english video learning platform based on FPGA system and sobel algorithm

In order to improve the system performance of image processing and improve the efficiency of image processing, we can use some hardware running image processing algorithms. in practice, we introduce some reconfigurable devices and more advanced programming languages to use FPGA for image processing. following will briefly introduce the design of FPGA in the edge detection system.The design has integrated a 32-bit soft RISC processor as dedicated hardware peripheral micro development and EDK embedded system developed by the system generator. Input is detected from a real-time image obtained from the CMOS camera displayed on the DVI display on the screen.

Enhancing network-on-chip performance by 32-bit RISC processor based on power and area efficiency

This papers deals with base design of the RISC-V 32b processor. It is used to support many additional commands including hardware loops, post-upgrade and save instructions and additional ALU instructions. RISC processors can be used in different ways, depending on speed and power consumption. Organized to design low power RISC processors through design and solution processes. The speed can also be increased by using the correct clock method. Decoding of execution, memory and rewriting. A one-sided clock signal is used for the middle stage. MIPS V adds a new data type, Single Associated (PS), which stores two single-point floating point numbers (32-bit) in a list of 64-bit floating point numbers. Existing floating point statement variants have been added for arithmetic operations, suitability and limitations to work with this type of data using the SIMD method. New instructions for downloading, transferring and transferring PS data have been added. This is the first command to skip the floating point SIMD with the available fonts.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

Low-cost, microcontroller-based, two-channel piezoelectric bender device for somatosensory experiments.

Understanding the joint encoding of multiple tactile stimulus features (e.g., spatial position, amplitude, and frequency of vibration) is a major goal of somatosensory neuroscience, and the development of experimental set-ups to probe joint encoding is important. We describe in detail a microcontroller-based, piezoelectric bender device for tactile experiments. The device comprises an Arduino Due microcontroller board with a 32-bit ARM Cortex-M3 RISC processor, and two 12-bit digital-to-analog converters, enabling precise, independent stimulation of adjacent epithelial points. Using laser doppler vibrometry, we developed a model of the benders' structural mechanics, which we implemented on the device. We used the device to delivered precise, reliable somatosensory stimulation in an experimental setting, recording electrophysiological responses in the peripheral nervous system of the Gisborne cockroach (Drymaplaneta semivitta) to sinusoidal vibration of tibial spines. We plotted tuning curves and derived bandwidths of multi-unit populations. We also stimulated rat facial vibrissae ex vivo. This microcontroller-based, low-cost, open-source system leverages a large developer community associated with Arduino, and may help speed advances in systems neuroscience.

Total-ionization-dose characterization of a radiation-hardened mixed-signal microcontroller SoC in 180 nm CMOS technology for nanosatellites

This paper presents design techniques and measurement results of a radiation-hardened mixed-signal microcontroller system-on-chip (SoC) dedicated to fully-customized nanosatellites for the civil active space debris (ADR) cleaning missions. The design requirements are firstly given. The architecture of an on-board computer (OBC) is then described. A radiation-hardened-by-design (RHBD) SoC is proposed for such applications to obtain a long operational period. The proposed SoC is composed of a dual-modular redundant (DMR) 16-bit RISC processor, a 1 kB SRAM, a 12-bit pipelined SAR ADC, a 12-bit current-steering DAC and an on-chip clock generator. The radiation-hardened-by-design techniques are adopted to resist the total-ionization-dose (TID) effects. An SoC prototype is designed and fabricated in 180 nm CMOS process. The electronical performance of devices-under-test (DUTs) has been measured based on a customized mother-daughter board. The performance of the proposed SoC meet the requirements of the nanosatellites. Furthermore, the TID radiation effect experiment is performed. It indicated that the proposed SoC can resist the total dose of more than 300 krad (Si) at the dose rate of 50 rad (Si)/s.

Pipeline Hazards Resolution for a New Programmable Instruction Set RISC Processor

The work presented in this paper is a part of a project that aims to concept and implement a hardwired programmable processor. A 32-bit RISC processor with customizable ALU (Arithmetic and Logic Unit) is designed then the pipeline technique is implemented is order to reach better performances. However the use of this technique can lead to several troubles called hazards that can affect the correct execution of the program. In this context, this paper identifies and analyzes all different hazards that can occur in this processor pipeline stages. Then detailed solutions are proposed, implemented and validated.

Floating accumulator architecture

Although technology advancement can pack more and more physical registers in processors, the numbers of architectural registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectural registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectural registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. In other words, the accumulator in FAA is an alias to some register in the register file at any instruction, and the alias relation can be dynamically updated by FAA at any program points. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized in two possible ways: doubling the number of ISA registers of modern 32-bit RISC processors or maintaining the number of ISA registers for 16-bit instructions on embedded processors. This paper presents the result of utilizing the free bit space to double the number of ISA registers from 16 to 32 on ARM processors, and experimental results show that performance can be improved by 7.6% on average for MediaBench benchmarks.

Design of a 16-bit RISC Processor Using VHDL

Design of a 16-bit RISC Processor Using VHDL

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

Background/Objective: Now a day’s electronics industry people are concentrating on low power designs. The growing market of portable electronic systems demands microelectronic circuit with ultra low power dissipation. Method: The accomplished operations in this design are logical operations, the arithmetic operations, and branch operations. The outcome values of these operations stored in the registers and they can retrieve from the same when needed. The low power RISC processor with unbiased double precision FPU is designed without any complication, because the power reduction can do in front end technique. Findings: On MAX V CPLD a low power pipelined 64-bit RISC processor is implemented. Arithmetic operations, logical and branch functions of RISC processor are successfully verified with this design. In order to avoid any misbehavior in the jump instructions, the data will flush in the pipeline automatically by the processor architecture. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. Modelsim software is used to verify the simulation results of the design. The ALU operations and double precision floating point arithmetic operation results will be displayed on 7-Segments.

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device. The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

DESIGN OF RISC PROCESSOR USING VHDL

The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan-3A XC3S50A XILINX Tool.

A NOVEL IMPLEMENTATION OF 32-BIT VLIW-MISC PROCESSOR ON FPGA

The main objective of this work is to implement a 32-bit pipelined RISC processor without interlocking stages. It is developed by S.I.M.E (Single Instruction Multiple Execution) that is with single instruction scheme more executions can be done and is based on VLIW(Very Long Instruction Word) architecture processing is an optimal choice in the attempt to obtain high performance level in Embedded Systems. In VLIW based architecture, the effectiveness of the processor depends on the ability of compilers to provide sufficient instruction level parallelism (ILP). The processor has been designed with VHDL, synthesized using Xilinx tool.

Design of a General Purpose 8-bit RISC Processor for Computer Architecture Learning

Computers are becoming indispensable for manipulating most everyday consumer products, ranging from communications and domestic electronics to industrial processes monitoring and control. High performance computer design is not only subject to the technology used for its implementation, it is also a matter of efficient training. The skills that must prevail in a good computer designer come from the type of courses taken and the tools employed during them. This work shows the design of an 8-bit RISC soft-core processor dedicated for a complete understanding of computer architecture. We consider this Processor an effective hands-on training solution for the comprehension of a computer from its lowest level up to testing.

Construction of hybrid autonomous and backup power supply for complex solar systems

The perspective hybrid autonomous and reserve power supply system, which is used in a complex heliosystems was developed by using of renewable energy sources in the form of photovoltaic panels, rechargeable batteries, charge controller and inverter, that converts the low-voltage constant current 12-24 V to the consumer standard ~ 220 V. This hybrid system was used in a complex heliosystems (in the case of unstable lighting the solar panels on the roof and walls simultaneously are disposed or on the East West are disposed etc.). Optimization (replacement) of the solar controller is the first step to the power generation increase by solar batteries, without solar panels adding. The most effective model of microcontroller unit for construction of a hybrid autonomous and emergency power supply system was investigated and developed by using of a Pulse-Width Modulation (PWM), as well as the solar battery Maximum Power Point Tracking (MPPT), which are used in a complex heliosystems maximum performance set up. This paper also consider the possibility to use of «intelectual» microcontrollers as control elements of microcontroller block to build an effective model of hybrid power supply system microcontroller unit for it maximum productivity setup. Microcontrollers with the MPPT technology of maximum power point tracking show a considerable advantages over other types of microcontroller block, such as low power microcontroller MPT612 with 32-bit RISC-processor ARM7TDMI-S.

Design and Implementation of 64-Bit RISC Processor for Industry Automation

In the era of industrialization, technological revolution reduced the intervention of humans to assist machinery. The privatization slogan has increased the competition among industries which leads to origin of new products/designs for automation. The paper presents, one such, design and implementation of 64-bit RISC processor on SOC for industry automation, mainly useful for packing of bottles in bottling plant. The design includes processor with BIST features; it is a mechanism that allows a machine to test itself. Here RISC processor is used to decrease the number of instructions and they execute the instruction at faster rate. Later the design is integrated on System on Chip (SoC) to obtain a single chip which reduces the overall power consumption. The design and synthesis is done by verilog and verified in cadence IUS and RTL compiler. The physical design is done by SoC encounter 11.10 version.