Abstract
The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan-3A XC3S50A XILINX Tool.
Highlights
The processors are characterized by nature of their instruction set architecture
RISC stands for reduced instruction set computer
As it is a RISC processor an instruction takes one clock to complete. It is simulated in Xilinx 13.1i ISE using VHDL and synthesized using Spartan-3A XC3S50A XILINX tool
Summary
The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan3A XC3S50A XILINX Tool. D. Mali, “DESIGN OF RISC PROCESSOR USING VHDL” International Journal of Research – Granthaalayah, Vol 4, No 6 (2016): 131-138
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