FPGA-Based Multi-Core MIPS Processor Design

doi:10.33103/uot.ijccce.21.2.2

Abstract

This research presents a study for multicore Reduced Instruction Set Computer (RISC) processor implemented on the Field Programmable Gate Array(FPGA).The Microprocessor without- Interlocked Pipeline Stages (MIPS) processor is designed for the implementation of educational purposes, as well as it is expected that this prototype of processor will be used for multimedia or big data applications. 32- bit MIPS processor was designed by using Very High speed Hardware Description Language (VHDL). Pipelined MIPS processor contains three parts that are : data path 32-bit MIPS pipeline, control unit, and hazard unit. The single cycle MIPS system was subdivided into five pipeline stages to achieve the pipeline MIPS processor. The five parts include: instruction fetch (IF), Instruction Decode (ID), execution (EXE), memory (MEM) and Write Back (WB). Three types of hazard: data hazard , control hazard and strctural hazard are resolved. Certain components in the pipelined stage for the design processor were iterated for four core SIMD pipelined processors. The MIPS is developed using Xilinx ISE 14.7 design suite. The designed processor was implemented successfully on Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA. The total power analysis of multi-core MIPS processor is obtanined 3.422 watt and the clock period was 7.329 ns (frequency: 136.444MHz). Index Terms— FPGA, MIPS, RISC, VHDL.

Highlights

Modern parallel computers use commodity processors, often multi-core, which allow parallel systems to have immediate access to rapid improvements in processing speed and energy efficiency [1]
The results show that the Microprocessor without Interlocked Pipeline Stage (MIPS) pipelined processor works on three times less power than MIPS non-pipelined
OVERVIEW OF PIPLENE AND MULTICORE MIPS PROCESSOR A Microprocessor without Interlocked Pipelined Stages (MIPS) is a type of Reduced Instruction Set Computer (RISC) architecture developed by computer systems

Summary

I.INTRODUCTION

Modern parallel computers use commodity processors, often multi-core, which allow parallel systems to have immediate access to rapid improvements in processing speed and energy efficiency [1]. [9] describes the a soft core five stages pipeline processor with a basic instructions set that can be changed on-demand due to the configurable nature of FPGA This processor improves the efficiency by using pipeline concept, because of the increase in development of the processor and System On Chips (SOCs). This system uses Xilinx ISE design 14.1 and Verilog language and was implemented on FPGA Xilinx Spartan 6 XC6SLX9-3CSG324. The results show that the MIPS pipelined processor works on three times less power than MIPS non-pipelined It uses Xilinx ISE software, Verilog VHDL code and implementation on Spartan 3E device XC3S500E.

OVERVIEW OF PIPLENE AND MULTICORE MIPS PROCESSOR A

PIPELINE MIPS PROCESSOR DESIGN

Hazard Detection Unit

PIPELINE INSTRUCTION SETS

SIMD INSTRUCTIONS FOR MULTICORE PROCESSOR

RESULTS