A novel technique for run-time loading for MIPS soft-core processor

Abstract

Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming an increasingly popular solution to support application-specific customization. However, any change in the assembly code of the implemented processor requires re-implement and download the soft-core on FPGA. This paper presents a FPGA realization of a run-time loading technique for a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) processor. The update of MIPS code is done without having to resynthesize, place and route, and reload the soft-core. The design consists of three main blocks: a microprocessor soft-core, a software tool and a universal asynchronous receiver/transmitter (UART). The software tools sets the content of the instruction memory space of the processor without having to go through the FPGA implementation process. The FPGA implements MIPS soft-core processor as well as the UART receiver. The software tool communicates with the softcore via UART. To demonstrate the proposed technique, we wrote an UP/DOWN counter assembly code. The design architecture is coded using Verilog based on top-down hierarchical design methodology and realized in Spartan-3E FPGA using Xilinx ISE 14.2. Based on the FPGA implementation results, the maximum operating frequency of the CPU is found to be 43.17 MHz.