32-bit Reduced Instruction Set Computer Research Articles

Design of Double 16_32 –Bit RISC Processor

Abstract: The SOCs built today offer a high level of functionality, serve a variety of applications, and improve in efficiency and cost. Embedded systems also face area and power consumption constraints in addition to real-time challenges. The main objective is to design and implement a 32-bit High-performance RISC (Reduced Instruction Set Computer) Processor architecture. The Processor is designed as an instantiation of submodules using Verilog HDL (Hardware Description Language). a 16-bit compatibility is introduced which makes use of the ISA to execute two 16bit operations at the same time and thus provides the capability to switch and execute both 32-bit and two 16-bit operations using the execution unit. The ISA is modified to meet the requirement to execute both 16-bit operation and 32-bit operations. Each of these instructions are independent of the other instruction and can be executed simultaneously. This enables the RISC based architecture to also enhance the speed of the design by a factor of 2 for 16 bit operations.

Indicator-based lightweight steganography on 32-bit RISC architectures for IoT security

Embedded devices with highly constrained resources are emerging in numerous application areas which include wireless sensor networks, Radio-Frequency IDentification (RFID) tags, and Internet of Things (IoT). These devices need to typically communicate small payload in the form of text/image/audio for which security is exceptionally essential. Considering the resource limitation on constrained devices, many crypto algorithms and a few stego algorithms have been designed with lightweight properties. Majority of these algorithms have been tested for lightweight property only based on their algorithmic attributes. Conversely, ensuring such lightweight characteristics by analysing their feasibility to reside and run in a constrained environment based on the device’s architectural attribute is inevitable for IoT applications. This paper aims to contribute by proposing an indicator based lightweight Least Significant Bit (LSB) steganography algorithm and to compare it’s algorithmic and device dependent implementation aspects with similar algorithms on popular 32-bit Reduced Instruction Set Computer (RISC) microcontrollers used in IoT platforms. The proposed variable embedding algorithm achieves a Peak Signal to Noise Ratio (PSNR) of over 46 dB with Normalised Cross Correlation (NCC) & Structural Similarity Index Measure (SSIM) being 0.9999 and 0.9998 respectively for an average embedding capacity of 1.5 bits per pixel. In addition to the above mentioned benchmarking parameter results, the Regular & Singular (RS) group and Sample Pair (SP) steganalysis, were also carried out to validate the security level of the proposed algorithm. On analysing the suitability of the proposed algorithm in terms of timing performance and memory requirements by implementing on different IoT hardware, the microcontroller with PIC32 core achieves a higher embedding throughput of over 2.7 Mega bits per second with a smaller memory footprint of less than 2 KB. Finally, the results obtained from the proposed work outperform the microcontroller implementation of stego algorithms reported in the literature.

Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

Real-Time Touch Controller with High-Speed Touch Accelerator for Large-Sized Touch Screens

For a large-sized touch screen, we designed and evaluated a real-time touch microarchitecture using a field-programmable gate array (FPGA). A high-speed hardware accelerator based on a parallel touch algorithm is suggested and implemented in this letter. The touch controller also has a timing control unit and an analog digital convert (ADC) control unit for analog touch sensing circuits. Measurement results of processing time showed that the touch controller with its proposed microarchitecture is five times faster than the 32-bit reduced instruction set computer (RISC) processor without the touch accelerator.

A multi-band OFDM ultra-wideband SoC in 90 nm CMOS technology

We present a multi-band orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) system on chip (SoC) for high speed wireless communications. The UWB SoC has a power management scheme to minimize the average power consumption and adopts hardware-efficient parallel processing architecture to reduce the logic gate count of the modem. Specifically, symbol synchronization block is implemented with the signed algorithm; automatic gain control (AGC), carrier frequency offset (CFO) estimation, and preamble delimitation check block share the eight complex multipliers during preamble transmission; and AGC, fast Fourier transform (FFT), symbol synchronization, CFO estimation, and preamble delimitation check blocks share the buffer which contains received symbols. This SoC adopts a 32-bit reduced instruction set computer (RISC) processor for high speed data transaction and supports universal serial bus (USB) 2.0 and secure digital input/output (SDIO) for host interface. The designed SoC is implemented with 90 nm CMOS technology with a core voltage of 1.2 V. The implemented chip size is about 5 mm x 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

A Real time ZigBee Based Locating System

Embedded Systems based on ARM processors are used extensively in mobile devices like PDA’s and MP3 players.ARM is 32bit Reduced Instruction Set Computer(RISC).Windows CE is real time, multi-task operating system that works on a 32-bit processor. This paper suggests Windows CE embedded operating system, and how to build a platform for Windows CE operating system embedded in a LS5310 ARM11 microprocessor S3C6410 and also the design of Windows CE embedded applications based on Embedded VC++ 4.0. Here we are employing RS232 serial port of ARM 11 processor and ZigBee wireless data communications module to design an application for a ZigBee location system with an easy-to-use interface. It performs multiple functions like information and data receiving, saving, processing and display. It has advantages of high performance, low cost, and low power consumption and is an important component of the network locating system.

MMV: A Metamodeling Based Microprocessor Validation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.

Design and Implementation of 160×192 Pixel Array Capacitive-Type Fingerprint Sensor

The application specific integrated circuit implementation of a capacitive fingerprint sensor system-on-chip (SOC), which embeds a 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of 160 × 192 array cells with a sensor detection circuit and an embedded 32-bit reduced instruction set computer (RISC) microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 80% more than conventional circuits and minimizes an electrostatic discharge influence by applying an effective isolation structure. The 32-bit RISC microcontroller is embedded by a latch base for low power and low complexity. The test chip was fabricated on a 0.35 μm standard complementary metal oxide semiconductor 1-poly 4-metal process.

Contents protection system using smart card interface for digital CATV network based on the opencable specification

In this paper, we have proposed the merging of the OpenCable reference model with the smart card interface defined by ISO/IEC 7816-3 and have implemented a new conditional access system (CAS) using this interface along with a Personal Computer Memory Card International Association (PCMCIA) interface. In addition, we have also designed the hardware architecture of the point-of-deployment (POD) security module, designed with the Verilog HDL, using the above two interfaces. The designed POD security module has an embedded 32-bit reduced instruction set computer (RISC) microprocessor that manages applications, such as an MPEG-2 filter, descrambler, and Data Encryption Standard (DES).

FRISC-E: a 250-MIPS hybrid microprocessor

A description is given of the FRISC-E, a 32-bit fast RISC (reduced instruction set computer) design using advanced differential bipolar logic. FRISC-E was designed to solve the problems caused by partitioning high-speed microprocessors, which is necessary to increase yield and reduce heat flux but requires die-to-die interconnections that cause signal propagation delays. The design and packaging of FRISC-E is described, and its use of pipelining is discussed. System architecture and performance are examined. >

Processor architecture considerations for embedded controller applications

The ways in which the environment of an embedded controller differs from that of a general-purpose CPU are described. A particular embedded controller application, the network interface is examined. The microprocessor used is the 32-bit VL86C010 Acorn RISC (reduced-instruction-set computer). The features of the network architecture, as they affect the choice of processor, are discussed. The impact of system latency on the choice of hardware is examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs implementation of a 32-bit RISC

This paper describes the efforts underway at McDonnell Douglas to design, fabricate, assemble and test a 32-bit reduced instruction set computer (RISC) using the enhancement mode junction field effect transistor (JFET) technology in Gallium Arsenide. The microprocessor is designed to operate at an average throughput rate of 100 million instructions per second (MIPS) with a pipelined add time which approaches 5 ns. These very high data rates place new requirements on the design of the computer. Time delays must be kept to a minimum. This implies that as many functions as possible must be included on the chip and that packaging will play a major role in the final computer. The CPU chip fabrication is being approached in stages, the initial stage was the fabrication of a full 32-bit ALU with associated registers and multiplexers, the second step is the fabrication of the full data path including the register file, three 32-bit internal buses and the ALU. The first circuit has been completed and the results are given. The second circuit is currently in fabrication.