300-mm Wafer Research Articles

Scalable transfer printing approach to heterogeneous integration of InP lasers on silicon-on-insulator waveguide platform

InP-based edge-emitting O-band lasers are integrated onto silicon photonics circuit employing micro-transfer printing technology. Blocks of unpatterned InP gain material of typical size 1000 × 60 μ m2 are first transferred onto 400 nm thick silicon rib waveguides with the fabrication steps performed on the target wafer to realize the final lasers. As a result, the InP ridge waveguides are aligned with lithographic accuracy to the underlying Si waveguides resulting in an approach free from any misalignment stemming from the transfer printing process. The fabricated Distributed Bragg Reflector laser shows lasing around 100 mA current injection with minimum 1 mW of output power coupled to a single mode fiber. This integration method paves a reliable route toward scaling-up the integration of active devices such as lasers, modulators, and detectors on 300-mm diameter silicon wafers, which requires high-uniformity across the wafer.

Leakage mechanisms of sub-pA InGaAs/GaAs nano-ridge waveguide photodetectors monolithically integrated on a 300-mm Si wafer

We report on a comprehensive temperature dependent dark current study of high-quality InGaAs/GaAs multi quantum well waveguide photodetectors monolithically integrated on silicon. They are integrated through metalorganic vapor-phase selective-area epitaxial growth in a 300 mm CMOS pilot line. Defects resulting from the metamorphic growth of III-V devices on Si make these devices susceptible to different leakage mechanisms at higher operating temperatures. For the high-temperature operation of complex photonics-electronics integrations, understanding the leakage mechanisms of the devices has critical significance. This will help to optimize designs promptly and ensure the reliability and longevity of such devices under extreme operating conditions. The photodetector devices exhibit dark currents below 1 pA, at room temperature and −1 V bias voltage, limited by the noise floor of the measurement setup. To resolve the different leakage mechanisms contributing to the dark current, the devices were measured at elevated temperatures and the results were cross-validated with device simulations. The devices exhibited very low dark currents, with a median below 0.1 nA at 195 °C, suggesting very high-quality material growth. Through device models, leakage mechanisms related to Shockley-Read-Hall (SRH) recombination at bulk volume defects are found to be the main factor contributing to the dark current. The surface SRH recombination is found to be limited, yet affecting the forward bias dark current due to the shortening of the diffusion paths of the majority carriers. Also, the device model shows that the actual dark currents at room temperature can be as low as 0.01 pA, more than 1-order lower than the measured levels. This study emphasizes the high quality of the III-V nano-ridge waveguide devices grown on Si, which can potentially expand the capabilities of silicon photonics platforms further.

Probing single electrons across 300-mm spin qubit wafers

Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid-state electronic devices1–3, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern complementary metal–oxide–semiconductor (CMOS) industry. Equally important, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics such as qubit yield and voltage variation. Spin qubits1,4,5 based on electrons in Si have shown impressive control fidelities6–9 but have historically been challenged by yield and process variation10–12. Here we present a testing process using a cryogenic 300-mm wafer prober13 to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and investigate the transitions of single electrons across full wafers. We analyse the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300-mm scale. Together, these results demonstrate the advances that can be achieved through the application of CMOS-industry techniques to the fabrication and measurement of spin qubit devices.

Cleaning and Particle Challenges in the Temporary Bonding and Debonding Process

The demands of 5G, Internet of Things and other global technology trends, combined with the increasing cost of scaling down process nodes, have created a shift towards more integrated packaging requirements. The emergence of advanced packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP), 2.5D/3D IC packaging, and heterogenous integration, brings potential for smaller form factors with increased functionality and bandwidth [1]. Backside processing or thinning of the device wafer is often needed for enabling these technologies. This requires the device wafer be adhered to a rigid carrier wafer using a temporary bonding material (TBM) for mechanical support during handling and processing. Following carrier release, the TBM must be thoroughly removed and cleaned from the device wafer. Many of these adhesives are exposed to high-power lasers or elevated temperatures, making removal more challenging. Sub-micron particle level clean demands for temporary bonding material (TBM) removal are also reaching standards typically reserved for front-end-of-line (FEOL) processing. This is especially crucial in 3D processes such as hybrid bonding where feature and pitch sizes are nearing <1 µm and insufficient cleaning can lead to failures in subsequent bonding processes [2]. Thus, careful consideration of all processing steps is necessary to meet stringent particle demands. This work investigates the removal of coated and baked TBM on silicon wafers, with an emphasis on processing conditions that obtain best particle results. Several chemistries were assessed at the beaker level by performing coupon-level studies and measuring surface properties. Based on these findings, studies with 300-mm wafers were performed using a customizable single-wafer processing tool.

Experimental and numerical analysis of wafer-to-wafer uniformity in double-sided polishing

Double-sided polishing (DSP) is a key process used to achieve super-flatness for 300-mm silicon wafers. Precisely controlling the uniformity of wafer thickness and flatness by DSP is important in advanced node-integrated circuit manufacturing. In this work, the dependence of variations in wafer-to-wafer thickness on wafer original thickness and carrier thickness was investigated. This research indicates that the thickness difference between the wafer and the carrier affects the deformation of the pad and thus changes the removal rate of material in the DSP process, which finally induces the non-uniformity. Besides, the platen shift caused by inconsistent original wafer thickness or carrier thickness is another key factor affecting wafer-to-wafer thickness uniformity. This work may provide guidance for producing high flatness uniformity wafers by optimizing the DSP process.

Study on the temperature field in the cutting zone for machining monocrystalline silicon wafer using free abrasive multi-wire saw

With increasing applications of integrated circuits, the requirements for the quality of the corresponding substrate silicon wafers have become more stringent. Slicing is a key step in the manufacturing of silicon wafers. At present, free-abrasive multi-wire saw (MWS) technology is commonly employed for substrate silicon wafer processing. However, the actual temperature field in the cutting zone is unclear because of the narrow cutting zone in multi-wire sawing. Although a simulation method was adopted in this study, the distribution of the slurry in the cutting zone remains ambiguous, causing a large difference between the simulation results. The temperature field is an important cause of warpage, which significantly affects wafer quality. In this study, an experiment and simulation of the temperature field in the cutting zone of a MWS of monocrystalline silicon with free abrasives were performed. First, an experiment was designed to measure the temperatures at different positions in the cutting zone. Then, based on the experimental data of the fluid pressure distribution and the temperature field in the cutting zone, after obtaining the heat source model, a simulation analysis was conducted, and the results are consistent with the experimental results. Finally, based on the heat flux model, the temperature field distribution in the cutting zone under different cutting conditions was simulated and analyzed. Temperatures of 36.7, 39.4, 40.7, and 42.8 °C were obtained at 22.5, 62.5, 137.5, and 177.5 mm, respectively, from the slurry entrance in the cutting zone. According to the heat source model based on the pressure distribution data of slurry in the cutting zone, the temperature values obtained via simulation at 22.5, 62.5, 137.5, and 177.5 mm from the slurry inlet were 35.4, 37.4, 41.5, and 43.1 °C, respectively. The maximum temperature difference is 1.8K°C, and the average temperature difference is 0.2K°C. Thus, the validity of the heat source model was verified. Further, based on the heat source model, the maximum temperature for cutting a 300-mm monocrystalline silicon wafer was predicted as 48.4 °C. Moreover, the wire speed was found to greatly influence the maximum temperature in the cutting zone. Tension also affects the temperature of the cutting zone, but to a lesser extent than the wire speed.

Exploration of Scandium Doping in SbTe for Phase Change Memory Application

In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{s}$ </tex-math></inline-formula> for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications.

Effect of Oxide Thickness by Metallic Residue during Radical Oxidation Using Vertical Batch-Type Furnace Equipment on 300-Mm-Diameter Silicon Substrates

Metallic residues have a detrimental effects on device performance as well as retard gate oxide growth rate to induce unintended thinner oxide layer. In this study, we found that oxide thickness could be subjective to metallic residues on the edge of silicon substrate. Hydrogen-assisted radical oxidation was investigated using vertical batch-type furnace equipment for a 300-mm wafer fab. Radical oxidation has been used to improve gate oxide quality overcoming the disadvantages of conventional wet or dry thermal oxidation for some applications. Since the radical oxidation method reduces dangling bonds and defects in the oxide layer due to activated oxygen radicals, a high-quality oxide film can be formed. It also helps improve reliability due to reduced dependence on the silicon crystal direction of oxidation, enabling uniform membrane deposition of stress-focused corner rounding oxidation. In addition, it has excellent throughput as it is possible to process up to 100 wafers simultaneously. This study has shown that as the number of wafers with metallic residues in the dummy pattern on the edge due to the wafer edge exposure (WEE) difference for each photo step increases in the same batch for radical oxidation, the median thickness has decreased. When the silicon wafer with the metallic residue was included within the same batch of the furnace equipment, the thickness of the oxide layer was reduced by 1.8% compared to when the metallic residue-free silicon wafer was included. The radical oxygen have a tendency to react to tungsten rather than silicon, which reduces the O2 value required to form SiO2 and lowers the thickness, which is due to the difference in electronegativity between silicon and tungsten, 1.9 and 2.36 respectively. The study is expected to improve gate oxide quality by controlling metal residues on the wafer edge or backside during the fab process.

(Invited) Nm-Scale Patterns and Selectivity: A Blessing or a Curse

Area-selective deposition (ASD) is a promising technique for semiconductor device manufacturing. The replication of nanoscale patterns by ASD can simplify device fabrication process flows by reducing the number of lithography, etch and chemical-mechanical polishing steps. In addition, ASD could eliminate pattern overlay errors. ASD is of special interest as device dimensions scale and has recently been shown as viable approach for the fully self-aligned via, to enable interconnect scaling beyond the 3 nm node [1]. However, the dependence of the selectivity of ALD and CVD processes on the patterning process and pattern dimensions is poorly documented. This aspect will be investigated in the current presentation. We will discuss the fundamental mechanisms of ALD growth mechanisms and how they influence selectivity. Next, we will discuss an example of Ru ASD with defect mitigation in nm-scale patterns on full 300-mm wafers [2].[1] Chen et al., IEDM21, 486-489.[2] Clerix et al., Adv. Mater. Interfaces 2021, 2100846.

High Speed X-ray Tomography with Submicron Resolution for FA and Reverse Engineering of Packages, PCBs, and 300 mm Wafers

Abstract This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

Electrical and Morphological Characterizations of 3-D Interconnections for Quantum Computation

Large-scale integration of quantum bits (qubits) requires 3-D architectures functional at sub-Kelvin temperatures. Electrical signals are transferred through 3-D interconnects to control and read out the information stored in the qubits. Careful design of the interconnects in terms of used materials and dimensions is, thus, essential to optimize the whole system performance. To help the design of future quantum architectures, we benchmark two interconnect technologies based on SnAg microbumps and Cu/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> hybrid bonding. We report electrical and morphological characterizations performed on 20- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch daisy chains (DCs) fabricated with die-to-wafer processes developed at CEA-LETI on 300-mm Si wafers. DCs with more than 20 000 SnAg microbump-based interconnects and more than 1000 direct Cu-bonded ones have been electrically characterized in a He <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> cryostat between 300 K and 500 mK. These measurements allow extracting unitary link resistances, establishing a preliminary process design kit at these low temperatures. The lack of defects and cracks on cross section electron micrographs performed after the low-temperature electrical measurements confirmed the mechanical robustness of these interconnect technologies to thermal variations between the room and sub-Kelvin temperatures.

Thickness Measurement Based on Eddy Current Sensor With Coaxial Double Coil for Chemical Mechanical Polishing

Real-time and accurate thickness measurements of copper films on 300-mm silicon wafers are utilized to improve global planarization, control polishing pressure, and avoid dishing and erosion caused by under-polishing and over-polishing during chemical mechanical polishing (CMP) of metals. Nevertheless, the requirements of nanometer-scale measurement sensitivity, wide measurement range from tens of nanometers to 2 μm, and high edge measurement performance make eddy-current thickness measurement extremely challenging. Therefore, we proposed a concise and effective theoretical model to analyze the measurement range and sensitivity in both the amplitude- and phase-based methods. The advantages and disadvantages of the two methods are compared and discussed systematically through simulations and experiments. The effects of the lift-off distance and frequency of excitation signal on measurement sensitivity, range, and edge measurement performance are also examined. The results show that the proposed theory can be used to improve measurement range and sensitivity. And the double-sensor system demonstrated better edge measurement performance than a single coil. Finally, a double-coil eddy current thickness measurement system designed with an average sensitivity of 1.9 mV/nm, a measurement range of 60 nm to 2 μm, and an edge attenuation position of 141.5 mm at a lift-off distance of 3.5 mm can be utilized in the amplitude-based method for advanced Cu-CMP.

Multi-field imprint technology: enabling the productivity enhancement of nano-imprint lithography

We have developed multi-field imprint (MFI) technology to improve the productivity of for nano-imprint lithography (NIL). Using a template having an imprinting size of 46 mm × 28 mm for MFI and the latest NIL system NZ2C (Canon Corp.), we successfully achieved MFI on a 300-mm wafer. The throughput being equivalent to 160 wafers per hour was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon and multi field dispense. The overlay accuracy around 7 nm was also obtained. In this report, we’ll report about the performance of MFI technology: patterning ability, throughput, and overlay accuracy, and discuss the future outlook.

Compact behavioral model and parametric extraction for optical phase shifters in carrier-depletion Mach–Zehnder silicon modulators

Testing of active photonic devices is totally different from testing of pure electronics; in particular, reduction of testing time in silicon photonics has been a significant issue. In this study, a compact behavioral model of optical phase shifters is constructed for carrier-depletion Mach–Zehnder (MZ) silicon modulators in the push–pull regime. The target characteristics, i.e., the dynamic extinction ratio (ER), absorption loss, and chirp parameter, are expressed in simple forms in terms of parameters representing the voltages-dependent modulation efficiency (ME) and the imaginary part of the effective index. The parameters reflecting manufacturing variability can be quickly extracted from fast DC measurements, which shortens the testing time. The theoretical concept relies on the proposal of a generalized form of the large-signal ME and an effective approximation for model construction that avoids the problem of the conventional small-signal definition being not applicable and large-signal definition leading to a cumbersome and non-intuitive formulation. It is shown that the constructed model suitably explains the physics and the reported experimental results for the slightly positive chirp characteristics of balanced phase shifters. Moreover, a parametric extraction applying the model is demonstrated in the C-band wavelength on a 300-mm SOI wafer.

Uniform deposition method of monodispersed SiO2 nanoparticles on a 300-mm Si wafer surface.

A study of the uniform deposition of nanoparticles across a 300-mm wafer was conducted to assess the uniformity of the wafer center-to-edge cleaning technique. A new method of particle deposition was devised different from the conventional method using electrostatic force. The strategy implements wafer rotation and deposition through principles of convection and diffusion. In this study, we focused on the effect of wafer rotation speed on particle deposition. After determining optimum conditions, fine results were obtained with a well-deposited shape and an excellent particle size uniformity of above 70% over the entire area of the wafer except in unusual cases. Deposition results were confirmed with KLA-Tencor Surfscan SP5 commonly used by foundries, and logic and memory manufacturers around the world to increase node development and production. The inherent indexof the refraction value by Surfscan SP5 caused a particle size shift in measurement results. However, scanning electron microscopy and scanning mobility particle sizer analysis results revealed that 80-, 60-, 40-, 30-, and 20-nm-sized silica nanoparticles were well deposited on the wafer. Through this research, we believe that standard wafers processed with this particle deposition method will be useful for performance evaluation of wafer cleaning technology and calibration of wafer inspection technology during development.

Loss-coupled DFB nano-ridge laser monolithically grown on a standard 300-mm Si wafer.

We present a loss-coupled distributed feedback microlaser, monolithically grown on a standard 300-mm Si wafer using nano-ridge engineering. The cavity is formed by integrating a metallic grating on top of the nano-ridge. This allows forming a laser cavity without etching the III-V material, avoiding damaged interfaces and the associated carrier loss. Simulations, supported by experimental characterisation of the modal gain of the nano-ridge devices, predict an optimal duty cycle for the grating of ~0.4, providing a good trade-off between coupling strength and cavity loss for the lasing mode. The model was experimentally verified by characterising the lasing threshold and external efficiency of devices exhibiting gratings with varying duty cycle. The high modal gain and low threshold obtained prove the excellent quality of the epitaxial material. Furthermore, the low loss metal grating might provide a future route to electrical injection and efficient heat dissipation of these nanoscale devices.

Spin Readout of a CMOS Quantum Dot by Gate Reflectometry and Spin-Dependent Tunneling

Silicon spin qubits are promising candidates for realizing large-scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly occupied gate-defined quantum dot, fabricated using CMOS-compatible processes at the 300-mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum-dot charge sensor, measured using rf gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5–0.7 meV using excited-state spectroscopy, and measure a maximum electron-spin relaxation time (T1) of 9±3 s at 1 T. These long lifetimes indicate the silicon-nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well suited to a variety of scalable architectures.4 MoreReceived 16 May 2020Revised 12 October 2020Accepted 24 February 2021DOI:https://doi.org/10.1103/PRXQuantum.2.010353Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.Published by the American Physical SocietyPhysics Subject Headings (PhySH)Research AreasQuantum computationPhysical SystemsQuantum dotsCondensed Matter, Materials & Applied Physics

Aledia Touts MicroLED Chip Progress

FRENCH STARTUP FIRM ALEDIA SAYS IT HAS MANUFACtured the first microLED chips using 300-millimeter (mm), or 12-in., silicon wafers. This development could pave the way for more widespread use of microLED technology in smartphones and televisions by leveraging established silicon foundry technology. Traditional LED chips have been produced using 100- and 150-mm (4- and 6-in.) sapphire wafers, upon which flat layers of gallium-nitride (GaN) crystal are deposited. Aledia, which was spun out of the French government-backed research institute CEA-Leti [Laboratoire d'électronique des technologies de l'information] in Grenoble in 2012, has spent the past eight years developing microLED technology for large-area silicon such as 200-mm (8-in.) silicon wafers. It recently used CEA-Leti's pilot lines to make the leap to 300-mm (12-in.) wafers. Aledia says its 3D nanowire technology grows GaN nanowires (GaN crystals of submicron diameter) on top of large-area silicon. According to the company, this doesn't create the stresses seen with the traditional flat-layer approach, as the wafer size is increased. That means its technology could be used to mass-produce microLEDs with the same 200- and 300-mm wafers used by high-yield silicon foundries today to make smartphone and computer processing chips. This also yields cost-effective integration with smaller-node electronics in the process. Volume chip manufacturing is essential for microLED's long-term success, where each pixel in the display is created by a microscopic LED. “We believe producing microLEDs on large-area 300-mm silicon wafers is a world's first, and opens this technology to huge potential-volume-manufacturing capabilities,” Aledia CEO and cofounder Giorgio Anania says in a press release. “The larger size allows 60 to 100 smartphone displays to be made on a single 300-mm wafer, versus approximately four-to-six using the present LED industry-standard, 4-in. sapphire substrate. Thanks to Aledia's unique nanowire LED technology [3D LED], this can be done with commercially available processes and equipment, since it uses standard-thickness [780 micrometer, or μm] silicon wafers.” Aledia has attracted big investors, including Intel Capital, and in 2019 it reached a process-development partnership with Israeli silicon foundry TowerJazz to commercialize its technology. Last fall, it raised $97 million for building its own microLED plant in Grenoble, which it aims to have operational by mid-2022. Aledia is certainly in a strong financial position, but may still be years away from mass-producing microLEDs on 12-in. wafers, says Yole Développement Senior Industry Analyst Eric Virey. He notes the company's development with TowerJazz to date has been confined to 8-in.-wafers and that Aledia worked with CEA-Leti researchers and used the institute's pilot line for the 12-in.-project, which he describes as being more in the research and development stage. microLED Chip WireLED on 300 mm (12 in.) silicon wafer. Source: Aledia However, one of the biggest roadblocks for microLED is cost, says Virey, and one way to address that is to reduce the LED chip's cost. So even moving to 8-in.-silicon production over smaller-format sapphire wafers would have a tangible benefit. “This opens the door to a vast amount of battle-tested 8-in. [complementary metal-oxide semiconductor] tools and CMOS fabs,” he says. “There are a lot of tools developed, more than anything for LED, and there are a lot of used tools for the grab. It would be a brave new world for microLED to get into the world of 8-in. silicon.” Overall, Virey forecasts a slow rollout for microLEDs in TV displays. Samsung has introduced a commercial 110-in. TV, but with a price tag of around $150,000, it's far from a mainstream consumer product. He says that if development goes well, we might see microLED TVs in the same price range as high-end OLED TVs in five or six years. “The goal of the industry for TV is they need to cut costs by a factor of 10 to 20,” says Virey. “There is a credible path to get there, but nobody is saying it's an easy path, and right now OLED and the other technologies are moving targets.” However, microLED looks more feasible for smaller displays. Virey notes that in 2021, Vuzix is commercializing the first augmented reality (AR) glasses that will use microLED, where its brightness is a big advantage. He expects Apple to start making its own microLED displays for the Apple Watch in late 2022, with commercial introduction probably coming in 2023. “They're only now in the process of building a real pilot line, and a lot will depend on the pilot line,” says Virey. “But that would be a serious disruption for the industry, if [Apple] would start making their own displays.” —By Glen Dickson

Tribological Characterization of Anionic Supramolecular Assemblies in Post-STI-CMP Cleaning Solution Using a Novel Post-CMP PVA Brush Scrubber

We have shown how different micellar (SDBS) vs. polyelectrolytic (PSSA) supramolecular assemblies in post-CMP cleaning solutions differ in their tribological performance when used in a novel PVA scrubber for 300-mm silicon dioxide wafer cleaning. Significant differences in real-time shear force and coefficient of friction data from the wafer-solution-brush interface (both in time domain as well as frequency domain) have been attributed to differences in each supramolecule’s chemical functionality and structure, which in turn, have been correlated to wafer-level defects. The work has underscored the importance of measuring the tribological attributes of post-CMP cleaning processes in an effort to improve cleaning performance.

Assessing Less-Tangible Benefits of an Ergonomic Project

The purpose of this study was to assess the less-tangible benefits of an ergonomics project performed in a 300-mm wafer fabrication in Taiwan. The studied project was aimed at reducing the risk factors of musculoskeletal disorders (MSDs) faced by the wafer-handling workers. Firstly, the MSDs checklist was used to identify risk factors for the workers. The ergonomic intervention was then conducted. Subsequently, the willingness-to-pay (WTP) survey of the contingent valuation method was performed to quantify less-tangible benefits. The responded WTP results were analyzed to estimate the return on investment of this project, which was 43.6% and large enough to conclude that this project was cost-effectiveness. The marked decreases in the risk-factor found rate and the self-reported MSD rate in the post-intervention period proved that the intervention was effective in reducing the MSD problems. This paper is shown to be a good example to justify the worth of an ergonomics project.