3-input Adder Research Articles

Optimal Constant Multiplication Using Integer Linear Programming

Constant multiplication circuits can be realized multiplierless by using additions, subtractions, and bit-shifts. The problem of finding a multiplication circuit with minimum adders and subtractors for a given constant (set of constants) is known as single (multiple) constant multiplication (SCM, MCM) problem. This brief proposes a novel integer linear programming (ILP) formulation to optimally solve SCM and MCM problems. In contrast to previous ILP approaches, none of the possible intermediate constants have to be pre-computed as all additions are directly evaluated. This leads to fewer ILP variables and more compact models. Due to the flexibility of ILP, the proposed model can be extended to several other (secondary) objectives. To demonstrate this, an extension for minimal SCM and MCM circuits using 3-input adders as well as an extension for minimizing the circuits' glitch path count for low power applications are provided. The experimental results show that the formulation is useful for practically relevant problem sizes.

Design for a multi-input binary adder

The need often arises in digital systems for a fast multi-input adder capable of adding together n distinct serial binary numbers. The normal design method is to employ a parallel-series configuration of 2-input synchronous adders. It is shown how the overall speed of a multi-input adder may be enhanced using a 3-input adder stage. A circuit is described using cascaded 2- and 3-input synchronous adders, which may be clocked at 100 ns allowing the addition of six 10-bit binary numbers in lµs.