28nm Field Programmable Gate Array Research Articles

A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net

A reconfigurable field-programmable gate array (FPGA)-based wired-logic deep neural network (DNN) accelerator is presented. High energy efficiency of 16 nJ/classification (Modified National Institute of Standards and Technology: MNIST) is achieved due to the wired-logic architecture. Each neuron in the neural network consists of combinational circuits only, and all the neurons are implemented on an FPGA. Intermediate data are never stored in memory or registers and are transmitted to the output stage by passing through only neuron cells. The latency and power required for memory access can be minimized, enabling low power and high throughput operation. A critical technical issue is reducing hardware resources because all neurons need to be implemented on an FPGA, where hardware resources are limited. Two core technologies have been developed to minimize the required hardware resources: (1) A neural network with a small number of neurons in which weight values of all synapses are fixed to a common value, and (2) a small neuron cell circuit consisting of an adder and look-up table containing an activation function. By fixing all weight values to a certain common value, processing can be simplified from multiply-accumulate operations to just additions, and the hardware resources required for each neuron are minimized. An experiment with the MNIST dataset using a 28-nm FPGA confirmed power consumption of 0.16 W and latency per inference of 100 ns (16nJ/classification). With the same recognition accuracy, the power efficiency is 45.6 times higher than that of the conventional state-of-the-art binarized DNN accelerator with a digital ASIC.

A Highly Linear FPGA-Based TDC and a Low-Power Multichannel Readout ASIC With a Shared SAR ADC for SiPM Detectors

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.

Time-to-Digital Converter IP-Core for FPGA at State of the Art

The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16).

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Proton- and Neutron-Induced Single-Event Upsets in FPGAs for the PANDA Experiment

Single-event upsets (SEUs) affecting the configuration memory of a 28-nm field-programmable gate array (FPGA) have been studied through experiments and Monte Carlo modeling. This FPGA will be used in the front-end electronics of the electromagnetic calorimeter in PANDA (Antiproton Annihilation at Darmstadt), an upcoming hadron-physics experiment. Results from proton and neutron irradiations of the FPGA are presented and shown to be in agreement with previous experimental results. To estimate the mean time between SEUs during operation of PANDA, a Geant4-based Monte Carlo model of the phenomenon has been used. This model describes the energy deposition by particles in a silicon volume, the subsequent drift and diffusion of charges in the FPGA memory cell, and the eventual collection of charges in the sensitive regions of the cell. The values of the two free parameters of the model, the sensitive volume side $d = 87$ nm and the critical charge $Q_{\text {crit}} = 0.23$ fC, were determined by fitting the model to the experimental data. The results of the model agree well with both the proton and neutron data and are also shown to correctly predict the cross sections for upsets induced by other particles. The model-predicted energy dependence of the cross section for neutron-induced upsets has been used to estimate the rate of SEUs during initial operation of PANDA. At a luminosity of $1\cdot 10^{31}$ cm $^{-2}\,\,\text{s}^{-1}$ , the predicted mean time between upsets (MTBU) is between 120 and 170 h per FPGA, depending on the beam momentum.

Digital instrument with configurable hardware and firmware for multi-channel time measures

A new digital instrument for timing of events is presented. It is based on a reconfigurable, high-performance, 16-channel time-to-digital converter implemented in a Xilinx 7 Series 28-nm field programmable gate array device. Each channel provides timestamps with a least significant bit of 2 ps that states the resolution, whereas instead the single-shot precision is below 12.5 ps rms with the possibility of multihit measures at the maximum rate of 20 MHz. The default width of the full-scale range is 157 µs that can be extended at users choosing up to 15 days by means of proper time tagging procedures made available. The instrument achieves performance in terms of precision, resolution, and full-scale range of measurement at the state-of-art of existing solutions. The novelty is that besides performance, the presented instrument is totally reconfigurable by the user both in the hardware and in the firmware parts. Moreover, novel techniques of event acquisition (e.g., level-zero trigger) are introduced. These further features are not present in any other instrument available nor in the literature or in commerce and constitute a difference with respect to all referenced instruments.

Highly Integrated FPGA-Only Signal Digitization Method Using Single-Ended Memory Interface Input Receivers for Time-of-Flight PET Detectors.

We propose a new highly integrated field-programm-able gate array (FPGA) only signal digitization method for individual signal digitization of time-of-flight positron emission tomography (TOF PET). We configured I/O port of the FPGA with a single-ended memory interface (SeMI) input receiver. The SeMI is a single-ended voltage-referenced interface that has a common reference voltage per I/O Bank, such that each SeMI input receiver can serve as a voltage comparator. The FPGA-only digitizer that uses the single-ended input receivers does not require a separate digitizing integrated chip, and can obtain twice as many signals as that using LVDS input receivers. We implemented a highly integrated digitizer consisting of 82 energy and 82 timing channels using a 28-nm FPGA. The energy and arrival time were measured using a 625-ps binary counter, and a 10-ps time-to-digital converter (TDC), respectively. We first measured the intrinsic characteristics of the proposed FPGA-only digitizer. The SeMI input receiver functioned as the voltage comparator without undesirable offset voltage. The standard deviation value of the time difference measured using two SeMI input receivers with respective TDCs was less than 14.6 ps RMS. In addition, we fed signals from the TOF PET detectors to the SeMI input receivers directly and collected data. The TOF PET detector consisted of a 3 × 3 × 20mm3 LYSO crystal coupled with a silicon photomultiplier. The energy resolutions were 7.7% and 7.1% for two TOF PET detectors. The coincidence resolving time was 204 ps full width at half maximum. The SeMI digitizer with a high-performance signal digitizer, processor, and high-speed transceivers provides a compact all-in-one data acquisition system.

Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures

Two field-programmable gate array (FPGA) designs are tested for dynamic single event upset (SEU) sensitivity on two different 28-nm static random access memory-based FPGAs—an Intel Stratix V and a Xilinx Kintex 7 FPGA. These designs were tested in both a conventional unmitigated version and a version to tolerate SEUs with feedback triple modular redundancy (TMR). The unmitigated design sensitivity and the low-level device sensitivity were found to be similar between the devices through neutron radiation testing. Results also show that feedback TMR and configuration scrubbing benefit both designs on both FPGAs. While TMR is helpful, the benefit of TMR depends on the design structure and the device architecture. TMR and scrubbing reduced dynamic SEU sensitivity by a factor of 4– $54\times $ .

Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA

Microfluidic cooling has been demonstrated as an effective means of cooling microelectronic circuits with a very low convective thermal resistance and potential for integration in close proximity to the area of heat generation. However, microfluidic cooling experiments to date have been limited to silicon with resistive heaters representing the heat generating circuitry. In this paper, a micropin-fin heat sink is etched into the back side of an Altera Stratix V field-programmable gate array (FPGA), built in a 28-nm CMOS process. Thermal and electrical measurements are made running a benchmark pulse compression algorithm on the FPGA. Deionized water is used as a coolant with flow rates ranging from 0.15 to 3.0 mL/s and inlet temperature ranging from 21 °C to 50 °C. An average junction-to-inlet thermal resistance of 0.07 °C/W is achieved.

A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations

This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the nonuniformity originated from carry chains, and use a multiphase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [−0.38, 0.87] LSB (the least significant bit: 10.5 ps) with $\sigma _{\mathrm {DNL}} = 0.20$ LSB, and the integral nonlinearity (INL) is within [−1.23, 1.02] LSB with $\sigma _{\mathrm {INL}} = 0.50$ LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNL $_{\mathrm {pk-pk}}$ (peak-to-peak DNL) and INL $_{\mathrm {pk-pk}}$ (peak-to-peak INL) can be reduced to 0.08 LSB with $\sigma _{\mathrm {DNL}} = 0.01$ and 0.13 LSB with $\sigma _{\mathrm {INL}} = 0.02$ LSB, respectively.

Buffer, Extraction and Style based RAM Design on 28nm Field Programmable Gate Array

In this work, we report a detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA).The designing of this memory circuit is done by Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Different RAM styles and RAM extracts are compared on basis of power consumption and reduction. Auto RAM style is the default RAM style and it consumes minimum power as compared to block RAM. The RTL schematic shows I/O ports, nets and primitives. Bufgdll also consumes less power and power reduction is also maximum for bufdll and auto RAM as compared to block RAM, ibufg and RAM extract yes. Auto RAM at 10GHz frequency can be used in designing various applications like in radio astronomy, microwave devices and communications, wireless LAN, most modem radars, communications satellites, satellite television broadcasting.

Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

Multiplier is used for multiplication of a signal and a constant in Digital Signal Processing (DSP). 28nm tech-nology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and Xpower Analyser. Vedic multiplier gains speed improvements by parallelizing the generation of partial prod-ucts with their concurrent summations. In this work, we are exploring the feasibility of Vedic multiplier in Data Encryption Algorithm, DSP, reliable system, multimedia and fault tolerant systems. In our work, we are using 11 different IO standards from HSTL (High Speed Transistor Logic) and LVCMOS (Low Voltage Comple-mentary Metal Oxide Semiconductor) family. IO standards are used to match the impedance of transmission line, input/output port and device. The energy-efficient multipliers play a significant role in portable computing and communication systems also. Here we are using Field Programmable Gate Array (FPGA) in order to re-duce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy efficient Vedic multiplier. There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively.

Enabling Manufacturable 3-D Technology and Ecosystems Using a 28-nm FPGA With Stacked Silicon Interconnect Technology

Technology challenges and solutions in the development and manufacturing of stacked silicon interconnect (SSI) technology have been investigated with the established foundry and outsourced semiconductor assembly and test ecosystem. Key enabling technologies, such as through-silicon-via processing, interposer backside manufacturing yield enhancement, new stacking technology, interposer warpage control, and microbump processes and joining, which are the building blocks for SSI technology, were developed. Xilinx's 28-nm field programmable gate array with an SSI technology platform was used to develop and optimize the seamless integration of the processes, structures, and parameters, as well as to evaluate their yield, reliability, and device performance.

Energy Power Efficient Vedic Multiplier Design on 28nm FPGA Using Vedic Formula ANURPYENA

The paper is about the designing of the low power energy proficient Vedic multiplier on 28nm field programmable gate array. Our motive here is to design a low power energy efficient design and for that reason, we are doing our study on different types of LVCMOS IO standards: LVCMOS_15, LVCMOS_18, LVCMOS_25, LVCMOS_33. To verify the thermal aware design we have taken 5 different temperatures from five different areas 10C, 25C, 40C, 55C, 70C. There is 3.73%, 3.21%, 3.005%, 3.002% reduction in leakage power, there is 0.544%,0.71%,3.63%,1.21% reduction in MAT and there is 73.74%,70.43%,52.00%,61.93% reduction in JT for LVCMOS_15, LVCMOS_18, LVCMOS_33, LVCMOS_25 correspondingly as we level down ambient temperature from 70 C to 10 C.

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing

With its reprogrammability, low design cost, and increasing capacity, field-programmable gate array (FPGA) has become a popular design platform and a target for intellectual property (IP) infringement. Currently available IP protection solutions are usually limited to protect single FPGA configurations and require permanent secret key storage in the FPGA. In addition, they cannot provide a commercially popular pay-per-device licensing solution. In this paper, we propose a novel IP protection mechanism to restrict IP's execution only on specific FPGA devices in order to efficiently protect IPs from being cloned, copied, or used with unauthorized integration. This mechanism can also enforce the pay-per-device licensing, which enables the system developers to purchase IPs from the core vendors at the low price based on usage instead of paying the expensive unlimited IP license fees. In our proposed binding-based mechanism, FPGA vendors embed into each enrolled FPGA device with a physical unclonable function (PUF) customized for FPGAs; IP vendors embed augmented finite-state machines (FSM) into the original IPs such that the FSM can be activated by the PUF responses from the FPGA device. We propose protocols to lock and unlock FPGA IPs, demonstrate how PUF can be embedded onto FPGA devices, and analyze the security vulnerabilities of our PUF-FSM binding method. We implement a 128-bit delay-based PUF on 28-nm FPGAs with only 258 RAM-lookup tables and 256 flipflops. The PUF responses are unique and reliable against environment changes. We also synthesize a variety of FSM benchmark circuits. On large benchmarks, the average timing overhead is 0.64% and power overhead in 0.01%.