Time-to-Digital Converter IP-Core for FPGA at State of the Art

Abstract

The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16).