50nm Gate Length Research Articles

Theoretical Study of Some Physical Aspects of Electronic Transport in nMOSFETs at the 10-nm Gate-Length

We discuss selected aspects of the physics of electronic transport in nMOSFETs at the 10-nm scale: Long-range Coulomb interactions, which may degrade performance and even prevent ballistic transport from occurring; scattering with high-k insulator interfacial modes, which depresses the electron mobility but is found to affect minimally the saturated transconductance of 15-nm devices; and the use of high-mobility small effective-mass substrates, which poses serious concerns related to performance limitations due to the density-of-states (DOS) bottleneck and to the band-to-band (Zener) leakage current. On the basis of our results, we argue that ballistic transport may not only be unachievable (because of unavoidable electron-electron collisions) but may also be undesirable, as it may enhance the DOS bottleneck. We also argue that the knowledge of low-field mobility is of little use in predicting quantitatively the performance of devices in the saturated region.

Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET

Dual-material-gate (DMG) insulated shallow extension gate-stack MOSFET involving dielectric pocket (DP) and DMG assimilation onto the conventional MOSFET has been studied. Simulations reveal a reduction in substrate leakage current, linearity improvement, enhancement in - g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , early voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EA</sub> ), and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , down to 50-nm gate length as an outcome of this DP and DMG integration.

N-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport

A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si1-yCy) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of Si1-yCy in the S/D regions. The carbon mole fraction incorporated is 0.013. Lattice mismatch of ~0.56% between Si 0.987C0.013 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron-mobility enhancement. The conduction-band offset DeltaEc between the Si0.987 C0.013 source and the strained Si channel could also contribute to an increased electron injection velocity nuinj from the source. Implementation of the Si0.987 C0.013 S/D regions for n-MOSFET provides significant drive current IDsat enhancement of up to 50% at a gate length of 50 nm

Room temperature tunable detection of subterahertz radiation by plasma waves in nanometer InGaAs transistors

The authors report on the demonstration of room temperature, tunable terahertz detection obtained by 50nm gate length AlGaAs∕InGaAs high electron mobility transistors (HEMTs). They show that the physical mechanism of the detection is related to the plasma waves excited in the transistor channel and that the increasing of the drain current leads to the transformation of the broadband detection to the resonant and tunable one. They also show that the cap layer regions significantly affect the plasma oscillation spectrum in HEMTs by decreasing the resonant plasma frequencies.

Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation

In this paper, a method to fabricate Silicon-on-Nothing (SON) MOSFETs using H+ and He+ co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.

Fabrication of p-type fin field-effect-transistors by solid-phase boron diffusion process using thin film doping sources

A simple doping method to fabricate a very thin channel body of the p-type fin field-effect-transistor (FinFET) with a 20-nm gate length by solid-phase-diffusion process is presented. Using the poly-boron-films (PBF) as a diffusion source of boron and the rapid thermal annealing, the p-type source/drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of boron-doped regions were investigated by using the p +–n junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20–100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

Analysis of the Transient Response of High Performance 50-nm Partially Depleted SOI Transistors Using a Laser Probing Technique

A new experimental technique is used to analyze the transient response of partially depleted SOI devices to pulsed laser irradiation. This new technique allows calibration of the deposited charge in the sensitive volume (i.e. the body region of the measured SOI transistors) and then the quantitative analysis of the device transient response. In particular 50-nm gate length SOI transistors have been tested with the pulsed laser, and their response is compared to 0.25-mum partially depleted SOI transistors. The transient current and the collected charge are investigated as a function of the supply voltage for both types of SOI devices. The technology' optimization for low leakage or high performance applications is shown to have large effects on the SOI device sensitivity.

Integration of components in a 50-nm pseudomorphic In0.65Ga0.35As–In0.40Al0.60As–InP HEMT MMIC technology

The basic active and passive elements for a 50-nm InGaAs–InAlAs–InP HEMT process with pseudomorphic InGaAs channel have been designed and realized. InP HEMTs with 50-nm gate length, metal–insulator–metal (MIM) capacitors and thin film resistors (TFRs) have been designed and fabricated. A 2×15μm HEMT showed an extrinsic peak transconductance of 1130mS/mm at a drain–source voltage of 2.0V. A 2×35μm HEMT exhibited a current gain cut-off frequency of 200GHz and a power gain cut-off frequency of 310GHz at a drain–source voltage of 1.1V. Passive device results included 85Ω/□ tantalum nitride TFRs and 300pF/mm2 Si3N4 MIM capacitors. The integration of the components in a microstrip-based monolithic microwave integrated circuit (MMIC) process has been demonstrated by designing, processing and testing of a wideband resistive feedback amplifier.

Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 /spl mu/m for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 /spl mu/A//spl mu/m for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

TCAD Modeling and Simulation of Sub-100nm Gate Length Silicon and GaN based SOI MOSFETs

AbstractSub-100nm gate length silicon and GaN based SOI n-type MOSFET are modeled and simulated using ISE-TCAD (now synopsys_sentaurus). Several silicon SOI structures such as planar fully depleted SOI, FinFET, Tri-Gate MOSFET, cylindrical channel (OMFET) and triangular channel MOSFETs have been studied to compare the structure dependence of the device performance. Silicon and GaN as channel materials are also compared for these different SOI structures for projecting the device performance for very short channel SOI MOSFETs. Our study shows that for sub-100nm gate length, GaN based transistors have better Ion/Ioff ratio and higher small signal transconductance than silicon based transistors. And GaN and Si based devices have comparable performance such as sub-threshold slope and threshold roll off, etc. However for sub 20nm gate length, simulation shows that while it is not satisfying for silicon based device for digital applications, GaN based transistors with lower off state leakage current, less short channel effect than Silicon based transistors are still good candidates for digital applications . The TCAD study shows that GaN could be a promising candidate for making very short channel device as the GaN processing technology is advancing.

Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-/spl mu/m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

This letter presents the first experimental study of the mobility in 50-nm gate length (L/sub G/) pMOSFETs highly strained by a contact etch stop layer. Thanks to an advanced characterization method, the mobility is in-depth studied versus the inversion charge density, the gate length and the temperature. The physical origin of the more than 50% mobility enhancement at L/sub G/=50 nm is proven to be the low effective mass of the top valence band rather than any scattering modification. This mobility gain is maintained even at high effective field. This explains the 30% I/sub ON/ enhancement at 50-nm gate length, which is among the best results at such a dimension.

Properties of Ta–Mo alloy gate electrode for n-MOSFET

As complementary metal oxide semiconductor (CMOS) devices are scaled beyond the 50-nm gate length node, the effective oxide thickness must be below 10 A to reduce short-channel effect and to improve device performance. Polysilicon has been extensively employed as a gate electrode, however, it has recently shown to suffer from instability on high-K dielectrics [1]. In addition, the inversion oxide thickness is increased by about 3–5 A due to polysilicon gate depletion [2]. Based on the above reasons, the investigation of metal gates is critical for scaling of advanced gate stacks [3]. Metal gate electrodes must have suitable work function, process compatibility and thermal/chemical interface stability with underlying gate dielectrics. In order to replace the polysilicon gate while maintaining the proper threshold voltage, work functions of the metal gates for n-channel MOS (NMOS) and p-channel MOS (PMOS) must be close to those of n+ and p+ doped polysilicon, which are close to 4 and 5 eV, respectively [4]. Metals with mid-gap work functions are known to be unsuitable for advanced CMOS devices due to severely degraded short channel characteristics [5]. While several thermally stable metals have been reported as possible gate electrodes for PMOS devices [6], metals having NMOS compatible work function typically suffer from thermal instability. Their high affinity towards oxygen promotes the reduction of the underlying dielectric and the formation of a metal oxide layer [7]. Binary metal alloys have been recently reported [6] and may provide a possible route for NMOS electrodes. In this work, we have investigated the electrical/material properties and thermal stability of a novel binary metal alloy, Ta–Mo, for NMOS gate electrode. Field oxide of 3500 A was grown to define active area on (100) p-type silicon substrate. The gate dielectric was 100 A SiO2 which was thermally grown at 900 . The binary metal alloys were deposited using a UHVPVD sputtering tool with a base pressure of 3 × 10−9 Torr. Sputtering was performed using a Ta target (purity of 99.5%) and a Mo target (purity of 99.95%). As shown

Optimization of the VT­control method for low-power ultra-thin double-gate SOI logic circuits

Application of the VT-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized VT-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.

Development of a Large-Scale TEG for Evaluation and Analysis of Yield and Variation

We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yield and variation for near-minimum DSM (deep sub-micron) design rules. We have successfully measured yield, failure mode and locations both before and after on-chip high-voltage stress. It was also demonstrated that intra-/inter-die variations in various process/device elements could be quickly diagnosed within a week. The new TEG consists of five chips designed using 130-nm CMOS technology with 100-nm physical gate lengths and five copper interconnect layers. The proposed TEG could provide a strategic standard test structure for diagnosis of SoC yield/variation, as well as a technology standard for measuring electrical dimensions and evaluating charge-up damage.

Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device Matrix Array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.

High-k gate stacks for planar, scaled CMOS integrated circuits

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moore’s Law towards the 10-nm physical gate length regime.

Negative differential resistance effects of trench-type InGaAs quantum-wire field-effect transistors with 50-nm gate-length

The effects of negative differential resistance (NDR) have been clearly observed in 50-nm-gate InGaAs/InAlAs trench-type quantum-wire (QWR) field-effect transistors (FETs), which are fabricated by atomic hydrogen-assisted molecular-beam epitaxy. The NDR onset voltage is as low as 0.1 V, and the highest peak-to-valley current ratio is 6.2 at 40 K. The equilateral symmetry of the NDR effect in a QWR FET is also observed. The pronounced NDR effects in a trench-type QWR FET are advantageous for high-speed and low power-consumption devices.