32-bit RISC Processor Research Articles

Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

Traditional application execution assumes an error-free execution hardware and environment. Such guarantees in execution are achieved by providing guardbands in the design of microelectronic processors. In reality, applications exhibit varying degrees of tolerance to error in computations. This paper proposes an adaptive guardbanding technique to combat CMOS variability for error-tolerant (probabilistic) applications as well as traditional error-intolerant applications. The proposed technique leverages a combination of accurate design time analysis and a minimally intrusive runtime technique to mitigate Process, Voltage, and Temperature (PVT) variations for a near-zero area overhead. We demonstrate our approach on a 32-bit in-order RISC processor with full post Placement and Routing (P&R) layout results in TSMC 45 nm technology. The adaptive guardbanding technique eliminates traditional guardbands on operating frequency using information from PVT variations and application-specific requirements on computational accuracy. For error-intolerant applications, we introduce the notion of Sequence-Level Vulnerability (SLV) that utilizes circuit-level vulnerability for constructing high-level software knowledge as metadata. In effect, the SLV metadata partitions sequences of integer SPARC instructions into two equivalence classes to enable the adaptive guardbanding technique to adapt the frequency simultaneously for dynamic voltage and temperature variations, as well as adapt to the different classes of the instruction sequences. The proposed technique achieves on an average <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$1.6 \times $</tex> </formula> speedup for error-intolerant applications compared to recent work <citerefgrp xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <citeref refid="ref33"/> </citerefgrp> . For probabilistic applications, the adaptive technique guarantees the error-free operation of a set of paths of the processor that always require correct timing (Vulnerable Paths) while reducing the cost of guardbanding for the rest of the paths (Invulnerable Paths). This increases the throughput of probabilistic applications upto <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$1.9 \times $</tex> </formula> over the traditional worst-case design. The proposed technique has 0.022% area overhead, and imposes only 0.034% and 0.031% total power overhead for intolerant and probabilistic applications respectively.

Core-A 플랫폼을 이용한 동기형 전력제어 임베디드 시스템 설계

본 논문은 마스터로 동작하는 32 비트 RISC 프로세서와 전력을 제어할 수 있는 다수의 슬레이브가 동기되어 동작하는 전력 제어 임베디드 시스템을 구현하였다. Core-A 플랫폼은 Core-A 프로세서, AMBA 버스, SSRAM, AC97, DMA, UART, GPIO모듈 등으로 구성된다. 슬레이브는 4 비트의 디지털 데이터의 값에 비례하여 220V 전력을 제어할 수 있는 아날로그 회로와 마스터가 보내는 신호에 동기되어 다양한 전력제어 패턴을 생성하는 제어 시스템을 설계 하였다. Core-A 플랫폼이 라이브러리로 구축된 Flowrian II를 사용하여 소프트웨어를 크로스 컴파일하고 하드웨어 회로를 시뮬레이션으로 검증하였다. 임베디드 시스템은 FPGA 검증 보드와 CPLD 칩에 구현되었고 전력제어 아날로그 보드를 제작하여 구현하였다. This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

Design methodology for on-chip-based processor debugger

Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

Design on Embedded Processor with Configurable Divider

By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) and Top-down methodology. The logic function was corrected by VCS simulation FPGA verification. Design Compiler synthesis result shows that, the maximal dominant frequency of the RISC embedded microprocessor could be up to 95MHz with the 0.18um CMOS process of SMIC, and is improved by 31.94% compared with STM32 Cortex-M3 (72MHz).

Design of Halt-Mode and Monitoring-Mode On-ChipDebugger 2G for Core-A

 Abstract—Nowadays, the SoC is concentrated by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. As the complexity of SoC design increases with technology development, the observability of the SoC's internal state is no longer easy to achieve. Because of the above reasons, debugging the SoC system becomes very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we deal with implementation of a hardware debugger named OCD2G which is based on IEEE 1149.1 JTAG standard and supports halt-mode and monitoring-mode debugging. In order to verify the operation of OCD2G, the designed debugger is integrated into the 32bit RISC processor - Core-A (Core-A is an embedded processor designed in South Korea) and is tested by interconnecting with software debugger.

The Design of Platform System for Measuring Bio-Signalwith Array Sensors

Platform system for measuring the bio-signal, especially Aptamer using array sensor is designed. This platform system is based on 32-bit RISC processor, AMBA bus, peripheral device and interface for array sensors. Array sensors measure a variation of capacitance value by reaction with Aptamer from bio-signal. Processor reduces noise from measured bio-signal and carries out bio-signal processing algorithm.

A novel hardware/software partitioning for SIMD-based real-time AVS video decoder

Decoding high-quality videos in real-time is becoming more and more difficult with the increasing resolution. In this paper, a novel hardware/software (HW/SW) partitioning is proposed with powerful SIMD (single instruction multiple data) instructions for the real-time AVS video decoder. Since most key functions that need large amounts of computations are optimized by SIMD instead of hardware, the distribution of workload between hardware and software is balanceable, and the performance of the video decoder is improved. Besides, the generality and programmability are also maintained. The proposed method is implemented on a 32-bit dual-issue RISC processor with 256-bit vector extension. The experimental results of conformation AVS test sequences show that the video decoder system can support the real-time decoding of AVS 1080p videos at 30 fps, and improve performance over 100 times compared to the original processor without the proposed method. Moreover, this approach could be easily applied to other video decoders, such as H.264 and VC-1.

Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi

In the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part. RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind of expandable, distributed large attendance logging system based on ARM Cortex M3 boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and HTML for man machine interface. This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol. The embedded board can act as a central CPU to communicate between web servers automatically.

FPGA Implementation of a 64-Bit RISC Processor Using VHDL

In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.&lt;em&gt; &lt;/em&gt;

Distributed data acquisition and control system based on low cost Embedded Web servers

In the present IT age, we are in need of fully automated industrial system. To design of Data Acquisition System (DAS) and its control is a challenging part of any measurement, automation and control system applications. Advancement in technology is very well reflected and supported by changes in measurement and control instrumentation. To move to highspeed serial from Parallel bus architectures has become prevalent and among these Ethernet is the most preferred switched Serial bus, which is forward-looking and backwardcompatible. Great stride have been made in promoting Ethernet use for industrial networks and factory automation. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities of cooling, maintenance etc. for slow speed field processing. A new kind of expandable, distributed large I/O data acquisition system based on low cost microcontroller based electronic web server[1] boards has been investigated and developed in this paper, whose hardware boards use 8-bit RISC processor with Ethernet controller, and software platform use AVR-GCC for firmware and Python for OS independent man machine interface. This system can measure all kinds of electrical and thermal parameters such as voltage, current, thermocouple, RTD, and so on. The measured data can be displayed on web pages at different geographical locations, and at the same time can be transmitted through RJ-45 Ethernet network to remote DAS or DCS monitoring system by using HTTP protocol. A central embedded single board computer (SBC) can act as a central CPU to communicate between web servers automatically.

Design and implementation of IAP techniques based on STM32F103VB

According to the requirements of firmware upgrade in embedded applications,the on-line software update solution based on the ARM Cortex-M3 32-bit RISC processor—STM32F103VB was given after introducing the feature of the In Application Programming(IAP) technique,and then the reliability of the solution was discussed.Finally,realization of on-line software update was given in detail.The solution realized on-line software upgrading based on STM32F103VB microprocessors in embedded applications,and shortened the development cycle and decreased the difficulty of maintenance for system software.

Realtime multiprocessor for mobile ad hoc networks

Abstract. This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with guaranteed bandwidth to the application that meets hard realtime requirements. At a clock frequency of 100 MHz the total power consumption of the MPSoC that has been fabricated in 180 nm UMC standard cell technology is 772 mW.

A matrix product accelerator for field programmable systems on chip

This paper presents a novel architecture for matrix multiplication optimized to be integrated as a coprocessor unit with embedded processors in modern FPGAs. In contrast with previous proposals that accelerate just the matrix multiplication computation, the coprocessor here proposed has been purposely designed to exploit an efficient communication protocol for the data exchange between it and the host processor that significantly reduces the whole computational time. The complete system formed by a 32-bit RISC processor augmented by the proposed coprocessor unit has been hardware implemented. Such system can be easily used to accelerate matrix multiplication with virtually any matrix sizes. Simulation tests and measurements demonstrate that the system requires a number of clock cycles more than halved, with respect to competitive solutions.

The Architecture and Development Flow of the S5 Software Configurable Processor

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study

This work presents a detailed case study in customizing a configurable, extensible, 32-bit RISC processor with vector/SIMD instruction extensions for the efficient execution of block-based video-coding algorithms utilizing a proprietary co-design environment. In addition to the default Full-Search motion estimation of the MPEG-2 Test Model 5, fourteen fast ME algorithms were implemented in both scalar and vector form. Results demonstrate a reduction of up to 68% in the dynamic instruction count of the full search-based encoder whereas the fast motion estimation algorithms achieved a reduction in instruction count of nearly 90%, both accelerated via three 128-bit vector/SIMD instructions when compared to the scalar, reference implementation of the standard. We address in detail the profiling, vectorization and the development of these vector instruction set extensions, discuss in depth the implementation of a parametric vector accelerator that implements these instructions and show the introduction of that accelerator into a 32-bit RISC processor pipeline, in a closely-coupled configuration.

Lowering power in an experimental RISC processor

Second year Computer Science students at the University of Manchester taking the VLSI Systems Design course complete the design of a 16-bit RISC processor down to silicon as the course laboratory exercise. Since the emphasis is on the design processes and testing, no especial effort is made to minimise power. This paper analyses the power dissipation of a typical pipelined design and then examines how the power efficiency might be improved at the architectural, RTL and logic levels. Simulation shows that the minimum dissipation is achieved by careful hand design; here, a factor of two improvement in the dissipation is achieved, with the major contribution being the logic level optimisation of the Register Bank to reduce the switching activity.

An AVS HDTV video decoder architecture employing efficient HW/SW partitioning

In this paper, we propose an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with HW/SW partitioning. AVS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32-bit RISC processor. We further propose the optimization of interface and RISC processor based on the proposed architecture. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5 MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60 fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board

New embedded digital front-end for high resolution PET scanner

This work describes a new digital front-end for a high-resolution low-cost animal PET scanner which is currently under development. The advances in flexibility and size of modern FPGAs together with the release of new tools enable the integration of most of the front-end electronics in a single FPGA. The implemented system includes a small 32-bit RISC processor, several peripherals attached to the internal buses and a special DSP unit closely attached to the processor which is dedicated to the detection of the gamma events. On top of these, a small footprint real time operating system abstracts the underlying hardware, providing the mechanisms to combine on-chip slow control and data streaming.

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.

Fast co-verification of HDL models

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog–VHDL models. Three benchmarks including a simple 32-bit processor (DP32), a 16-bit arithmetic RISC processor, and a 256-point FFT unit were used in the experiments. The experimental results show that the co-verification approach gives up to 15,000 times speedup for gate-level and up to 100 times speedup for RTL abstractions as compared with the simulation-based verification. Finally, an analytical study on the speedups of the co-verification approach is also presented, which supports the experimental speedups results.