Abstract

Abstract. This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with guaranteed bandwidth to the application that meets hard realtime requirements. At a clock frequency of 100 MHz the total power consumption of the MPSoC that has been fabricated in 180 nm UMC standard cell technology is 772 mW.

Highlights

  • Portable electronic devices like PDAs, mobile phones and notebooks are increasingly equipped with wireless communication technologies, providing higher degrees of mobility and ease of use

  • We developed different test cases to test the functionality of each processing element, the on-chip memories, the switch-boxes, the interface to external memory, the NoClinks and the physical ports

  • In this work we have presented a generic, scalable architecture for Multiprocessor SoCs (MPSoC) intended for low power wireless applications as mobile ad hoc networks

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Summary

Introduction

Portable electronic devices like PDAs, mobile phones and notebooks are increasingly equipped with wireless communication technologies, providing higher degrees of mobility and ease of use. Mobile ad hoc networks (MANETs) are a special type of wireless networks that do not require any infrastructure and whose topology can change spontaneously by the movement of participating nodes. To evaluate the performance and energy efficiency of new routing algorithms, especially including directional communication (Grünewald et al, 2005b) and transmission power control (Xu et al, 2005), we use the network simulator SAHNE (Volbert, 2002), see Fig. 1. This environment emulates the packet processing of each participating node.

Architecture of the multiprocessor
The Network-on-Chip
The Processing Element
Prototyping environment
The multiprocessor ASIC
Testing the SoC
Ressource consumption
Conclusions

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