28nm FDSOI Research Articles

A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias

This work presents a 16kB ultra-low power (ULP) SRAM macro in 28nm FD-SOI with high energy efficiency in active mode and ultra-low leakage (ULL) in sleep mode, embedded in the SleepRider micro-controller unit (MCU) intended for IoT edge applications. The proposed SRAM integrates custom 7T ULL bitcells based on negative differential resistance (NDR) structures and a pMOS-only write port, achieving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> lower area than previous NDR-based bitcells. A dual-supply strategy combined with negative-wordline write-assist concurrently provides worst-case data retention and correct write operations, up to the 64-MHz MCU target frequency. The SRAM macro periphery combines several low-power techniques to extract the full potential of the novel 7T bitcells, reaching an unprecedented speed-energy-leakage optimum with only 2.5% area overhead. Adaptive forward body biasing (FBB) further improves active mode performance while ensuring robustness against PVT variations. Measurement results showcase a minimum energy point of 0.78pJ per 32b access (assuming 50% read/write) at 0.5V and 64MHz. Moreover, leakage power drops from 296nW/kB at 0.5V in idle conditions to 0.23nW/kB in sleep at the 0.46V data retention voltage (DRV), yielding more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000\times $ </tex-math></inline-formula> leakage reduction. As such, the proposed SRAM achieves an excellent trade-off between area, leakage and energy in the 10-to-100MHz frequency range.

HW/SW Codesign for Approximation-Aware Binary Neural Networks

Binary Neural Networks (BNNs) are rapidly gaining remarkable attention due to their superiority in shrinking the model size, which outstandingly mitigates the fundamental “memory wall” bottleneck that is attributed to the existing von-Neumann architectures. This work investigates how principles from approximate computing can be effectively employed to further optimize BNNs. It demonstrates that HW/SW codesign, in which BNNs are either proactively trained in the presence of approximation-induced errors (i.e. design-time optimization) and/or augmented with an appropriate error-mitigation scheme (i.e., run-time optimization), is a key to realize energy-efficient yet robust BNNs. We unveil, for the first time, that although the underlying HW of BNNs can be implemented using simple <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">XNOR</monospace> gates, the complexity of the required “Popcount” circuit super-linearly grows with the filter kernel size. This largely impacts the area footprint, inference time, energy, and hence it severely constricts the prospective efficiency gains from BNNs. To overcome this challenge, we replace the accurate full adders constructing the Popcount with Majority gates that approximately perform the required additions. Then, our carefully-crafted error-mitigation scheme along with activations tuning considerably minimizes the induced errors. Afterward, abstracted error probabilities are derived and employed during BNN training to obtain approximation-aware BNNs, that are inherently robust against the underlying HW approximation. Differently from the typical approaches, the proposed HW/SW codesign methodology has the merit of allowing a training of the approximate BNN without the need to modify the existing software frameworks (i.e., PyTorch). This is of great importance since existing tools rely on efficient built-in functions that can be difficult and/or inefficient to be modified. An FPGA-based SoC realizing both accurate and approximation-aware BNNs is developed for validating our proposed methodology. With merely a 4.7% loss in the inference accuracy, our HW/SW codesign leads to 64% and 80.2% savings in the area and energy, respectively, at the parity of the latency. Our results are obtained using commercial EDA tool flows employing a commercial 28nm FDSOI technology node.

A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios

We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – 332 μW) for the digital signal processing of the software-defined radios.

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process nodes, leading to frequent power-hungry refresh operations. In order to reduce the refresh overhead, GC-eDRAM macros utilize external assist voltages which improve the bitcell write-ability, leading to an enhanced DRT. However, the requirement for external analog supply voltages creates additional overhead and is often impractical in the design of compact systems-on-chip (SoC). This work presents an on-chip write-assist technique implemented with a negative boosted bootstrap driver which generates the required wordline boosting on-chip without external components. The proposed circuitry is integrated compactly inside the GC-eDRAM macro to provide an area-efficient low-power solution which improves the bitcell’s write-ability and reduces its refresh requirement. A 128-kbit GC-eDRAM macro utilizing the proposed boosting circuitry has been fabricated in a 28-nm FD-SOI technology, demonstrating an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.3\times $ </tex-math></inline-formula> DRT improvement at only 2.5% area overhead.

A 62-GHz High-Efficiency Power Amplifier With Modulation Capability via Back-Gate in 22-nm FD-SOI

This letter presents a feasibility study for a 62 GHz power amplifier (PA) in a 22 nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages, and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm and a peak PAE of 28.3%. The PA consumes 96 mW from a 2 V VDD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids AC ground, gain and stability problems caused by conventional front-gate switching. In off-mode it draws 2.5% of its peak DC power. Rise-and fall-times of 1 ns were measured. The possibility of back-gate based modulation was experimentally demonstrated, showing that the PA can be used as a single device transmitter. Compared to previously reported works the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60 GHz PA with data modulation via the back-gate.

Mix &amp; Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Mix &amp; Latch</i> , a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive- and negative-edge-triggered flops, and positive- and negative-level-sensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a 28nm CMOS FDSOI technology, obtaining 1.33X post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than 1.19X on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance.

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation

In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-Magnetic-Tunnel-Junction (10T2DMTJ) non-volatile (NV) ternary content-addressable memory (TCAM) with sub-nanosecond search operation. Our cell design relies on low-energy-demanding MTJs organized in a low-complexity voltage-divider-based circuit along with a simple dynamic logic CMOS matching network, which improves the search reliability. The proposed NV-TCAM was designed in 28nm FDSOI process and evaluated under exhaustive Monte Carlo simulations. When compared to the best previous proposed NV-TCAMs, our solution achieves lower search error rate (3.8×) and lower write and search energy (–73% and –79%, respectively), while also exhibiting smaller area footprint (–74%). Such benefits are achieved at the expense of reduced search speed.

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

A Walsh-Based Arbitrary Waveform Generator for 5G Applications in 28nm FD-SOI CMOS Technology

A Walsh-Based Arbitrary Waveform Generator for 5G Applications in 28nm FD-SOI CMOS Technology

An LO phase shifter with frequency tripling and phase detection in 28 nm FD-SOI CMOS for mm-wave 5G transceivers

This paper presents an LO phase shifter with frequency tripling for 28-GHz 5G transceivers. The phase shifting and frequency tripling are achieved using an injection-locked oscillator and injection-locked frequency tripler, respectively. A phase detector based on third harmonic mixing is also implemented and is used to detect the applied phase shift, supporting automatic calibration of the phase shifter. Additionally, an algorithm to automatically tune the oscillators to their respective locking frequency is presented. To test the phase shifter, a 24–30-GHz sliding-IF receiver is implemented. Simulations show that a > 360^circ tuning range over the full 24–30 GHz span is achieved, with a gain variation of 0.11 dB or less, and that the phase detector has an rms phase error of < 2.5^circ . The circuit is implemented in a 28nm FD-SOI CMOS process and the entire chip measures 1080 upmu hbox {m}times 1080 upmu hbox {m}, including pads, and consumes 27–29 mW from a 1 V supply.

Narrow-Width Effects in 28-nm FD-SOI Transistors Operating at Cryogenic Temperatures

In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{m}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.08 ~\mu \text{m}$ </tex-math></inline-formula> at temperatures ranging from T = 300 K down to T = 10 K. We report, for the first time, the alarming concerns that the narrow-width effect imposes on the overall performance of highly scaled FD-SOI technologies, at temperatures below T = 77 K. The performance comparison between nMOS and pMOS devices is based on their drain current, threshold voltage, transconductance, subthreshold slope, low field mobility and total resistance. Our results show that the sensitivity of narrow width effects towards drain current, threshold voltage and total resistance is smaller in pMOS as compared to nMOS. The effective improvement in transconductance is also significantly larger in narrow width pMOS in comparison to their nMOS counterparts. A substantial degradation of subthreshold swing, total resistance and low field mobility is also observed in narrow nMOS devices, which questions the width scaling benefits of these technologies at cryogenic temperatures.

Total Ionizing Dose Impact on 22-nm FD-SOI Ring Oscillator Current and Frequency

Total ionizing dose (TID) has a significant effect on silicon-on-insulator (SOI) circuits, manifesting primarily as a front-gate threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> ) shift. This article presents data on ring oscillator (RO) responses of 22-nm fully depleted (FD-SOI) thin oxide (core logic) devices to gamma-ray doses above 1 Mrad(Si). We show large current and frequency TID response differences between ROs comprised of different logic gates. Moreover, the extensive experimental results presented here show that these responses vary significantly with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> and well type. The measurements show that depending on the expected dose and transistor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> used, TID-induced standby current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {SB}}$ </tex-math></inline-formula> ) increases may have a substantial impact on overall power in spaceborne integrated circuits (ICs) using this fabrication process. The TID impact on digital circuit timing margins is also discussed.

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067mm2, while the proposed linearity enhanced part is 0.05×0.02mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.

Beyond 100 Gbit/s Pipeline Decoders for Spatially Coupled LDPC Codes

Low-density parity-check (LDPC) codes are a well-established class of forward error correction codes that provide excellent error correction performance for large code block sizes. However, for throughputs toward 1 Tbit/s, as expected for B5G systems, state-of-the-art LDPC soft decoders are restricted to short code block sizes of several hundred to thousands of bits due to routing congestion challenges, limiting the overall communications performance of the transmission system. Spatially coupled LDPC (SC-LDPC) codes and respective sliding window decoding methods show the potential to overcome these block size restrictions. However, in contrast to conventional LDPC codes little literature exists on the efficient hardware implementation of respective high-throughput decoders. In this work, we present the first in-depth investigation on the implementation of SC-LDPC decoders for throughputs beyond 100 Gbit/s. For an N=51328, R=0.8 terminated SC-LDPC code with sub-block size c=640 and coupling width m_s=1, we explore various design trade-offs, including row- and column-wise decoding, non-overlapping and overlapping window scheduling, and processor pipelining. To the best of our knowledge, this is the first description of a column-wise SC-LDPC decoding architecture in the literature. We complement the algorithmic investigation with the virtual silicon implementation of all presented decoders in a 22nm FD-SOI technology.

A Stacked Segmented Adaptive Power Amplifier in 22nm FD-SOI

This letter presents a two-stage mm-wave power amplifier (PA) in 22nm fully depleted silicon-on-insulator (FD-SOI) technology. High output power is obtained through transistor stacking. Transistor segmentation and back-gate bias control techniques are used in this adaptive PA which can work in high gain mode (HGM) and high linearity mode (HLM). The proposed PA achieves 17.9 dBm saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{s}at$ </tex-math></inline-formula> ), 27.6 dB power gain, 11.6 dBm output 1-dB compression point (OP1dB), and 11.0% peak power-added efficiency (PAE) at 74 GHz in the HGM. In the HLM, 17.1 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{s}at$ </tex-math></inline-formula> , 21.2 dB power gain, 14.6 dBm OP1dB, and 12.9% peak PAE are obtained at 74 GHz.

Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies

Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.

A sub-30 GHz differential-frequency tripler in 22-nm FDSOI technology for FMCW spectrum

In this work, a wide-band Frequency-Tripler is designed to cover Frequency-Modulated Continuous Wave radar (FMCW) in 22-nm CMOS-FDSOI Technology. The designed frequency Tripler upconverts sub-30 GHz signal to cover a wide-band FMCW spectrum (72–84 GHz). In this paper, the silicon validated results of a VCO combined with the proposed frequency Tripler are presented. The design architecture, EM simulation results, measurement setup and silicon result of our fabricated die are covered in this paper. The designed circuit consumes 20 mA of current at the supply voltage of 800 mV. The Tripler works in the input frequency range from 24 GHz to 32 GHz, delivering a wide-band frequency output of 72–96 GHz. The differential output of VCO is capacitively coupled with the input of the multiplier.

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving &lt; −44-dBc HD3 Up To 1.5-Vp-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows <-44-dBc third harmonic distortion (HD3) up to 1.5-V <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>${_{{p-p}}}$</tex> </formula> output swing over 0.01-5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and ±5°, respectively. The chip is powered from a 5-V supply and dissipates 925 mW.

A mm-Wave Switched-Capacitor RFDAC

This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {{P_{\mathrm{ out}}}}&gt;21$ </tex-math></inline-formula> dBm, drain efficiency >36%, and system efficiency >22% while operating in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ka</i> -band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).

A Continuously-Scalable-Conversion-Ratio Step-Up/Down SC Energy-Harvesting Interface With MPPT Enabled by Real-Time Power Monitoring With Frequency-Mapped Capacitor DAC

An energy-harvesting interface that incorporates a continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) dc-dc converter with maximum power point tracking (MPPT) is introduced in this paper. By exploiting unique characteristics of a CSCR SC converter, an MPPT based on the hill climbing algorithm is implemented with a real-time power monitoring scheme with a frequency-mapped sampling capacitor DAC, allowing variation-tolerant MPPT for various types of energy sources. The harvestable voltage range is significantly extended by a step-up/down convertible CSCR SC converter, and the voltage conversion efficiency is further improved with matrix-structured and load-mapped power switches. With the test chip fabricated in 28nm FDSOI technology, the proposed energy harvesting interface shows peak conversion efficiency of 89% and average efficiency of > 80% for 60-2, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$794~\mu \text{W}$ </tex-math></inline-formula> . MPPT efficiency of > 97 % is confirmed with energy harvesting measurement with a solar cell.