12-inch Wafer Research Articles

DeepSEM-Net: Enhancing SEM defect analysis in semiconductor manufacturing with a dual-branch CNN-Transformer architecture

Due to the increasing complexity of modern semiconductor integrated circuit fabrication processes, various defects may occur at each process step, leading to a semiconductor integrated circuit yield loss as well as reliability problems. This study introduces DeepSEM-Net, a novel dual-branch architecture that harmoniously integrates Convolutional Neural Networks (CNN) with Transformers. This innovative approach significantly enhances defect classification and precise segmentation in Scanning Electron Microscope (SEM) defect images, crucial for semiconductor manufacturing processes. DeepSEM-Net consists of a classification branch, which synergizes CNN and Transformers for robust global feature extraction, and a segmentation branch, which incorporates a Pyramid Attention module to meticulously recalibrate and exploit the feature map, thereby enriching the segmentation quality. A semi-supervised defect analysis system based on this model markedly reduces manual inspection efforts and is adept at operating in both simultaneous and sequential classification-segmentation modes. Rigorously tested on a diverse dataset from a real 12-inch wafer fab, DeepSEM-Net not only demonstrated a commendable classification accuracy of 97.25% on a 5-class dataset and a segmentation IoU of 84.40% but also exhibited remarkable resilience against the introduction of new defect classes in an unbalanced dataset. The dual-branch strategy of DeepSEM-Net, thus, significantly elevates the efficiency and reliability of SEM defect image analysis, offering a substantial leap forward in addressing yield loss and ensuring the reliability of semiconductor products.

Silicon-Lattice-Matched Boron-Doped Gallium Phosphide: A Scalable Acousto-Optic Platform.

The compact size, scalability, and strongly confined fields in integrated photonic devices enable new functionalities in photonic networking and information processing, both classical and quantum. Gallium phosphide (GaP) is a promising material for active integrated photonics due to its high refractive index, wide bandgap, strong nonlinear properties, and large acousto-optic figureof merit. This study demonstrates that silicon-lattice-matched boron-doped GaP (BGaP), grown at the 12-inch wafer scale, provides similar functionalities as GaP. BGaP optical resonators exhibit intrinsic quality factors exceeding 25,000 and 200,000 at visible and telecom wavelengths, respectively. It further demonstrates the electromechanical generation of low-loss acoustic waves and an integrated acousto-optic (AO) modulator. High-resolution spatial and compositional mapping, combined with ab initio calculations, indicate two candidates for the excess optical loss in the visible band: the silicon-GaP interface and boron dimers. These results demonstrate the promise of the BGaP material platform for the development of scalable AO technologies at telecom and provide potential pathways toward higher performance at shorterwavelengths.

Ductile deformation and subsurface damage evolution mechanism of silicon wafer induced by ultra-precision grinding process

In the field of advanced packaging, large-size silicon wafers are usually thinned by ultra-precision grinding technology relying on the process of workpiece self-rotation. However, the damage caused by mechanical material removal deteriorates the wafer surface flatness and die strength, while its atomic-scale formation principle has yet to be revealed. This work explores the ductile deformation and subsurface damage evolution mechanism of silicon wafer during the ultra-precision grinding process. Some grinding tests are first conducted using different diamond wheels. The surface topography and energy dispersive spectroscopy (EDS) mapping of ground wafers are measured by scanning electron microscope (SEM). The phase transition properties of the ground silicon wafer are confirmed via Raman spectrum. Next, the specimen of groove cross-section is fabricated and its morphology is examined via transmission electron microscopy (TEM) to analyze the subsurface damage characteristics. The subsurface defects at the atomic scale, involving amorphous layer, dislocations, stacking faults and lattice distortions, are observed. Due to its controllable load and similarity of the cutting motion, nanoscratch is utilized for investigating the influence of abrasive interactions on subsurface deformation during the grinding process. Thus, a series of multiple nanoscratch tests are performed in both varied and constant force modes. The material removal behaviors under different scratching conditions are illustrated. This work provides a fundamental understanding of developing a high-efficiency and low-damage thinning method for 12-inch silicon wafers.

Modularized batch production of 12-inch transition metal dichalcogenides by local element supply

Two-dimensional (2D) transition metal dichalcogenides (TMDs) are regarded as pivotal semiconductor candidates for next-generation devices due to their atomic-scale thickness, high carrier mobility and ultrafast charge transfer. In analog to the traditional semiconductor industry, batch production of wafer-scale TMDs is the prerequisite to proceeding with their integrated circuits evolution. However, the production capacity of TMD wafers is typically constrained to a single and small piece per batch (mainly ranging from 2 to 4 inches), due to the stringent conditions required for effective mass transport of multiple precursors during growth. Here we developed a modularized growth strategy for batch production of wafer-scale TMDs, enabling the fabrication of 2-inch wafers (15 pieces per batch) up to a record-large size 12-inch wafers (3 pieces per batch). Each module, comprising a self-sufficient local precursor supply unit for robust individual TMD wafer growth, is vertically stacked with others to form an integrated array and thus a batch growth. Comprehensive characterization techniques, including optical spectroscopy, electron microscopy, and transport measurements unambiguously illustrate the high-crystallinity and the large-area uniformity of as-prepared monolayer films. Furthermore, these modularized units demonstrate versatility by enabling the conversion of as-produced wafer-scale MoS2 into various structures, such as Janus structures of MoSSe, alloy compounds of MoS2(1−x)Se2x, and in-plane heterostructures of MoS2-MoSe2. This methodology showcases high-quality and high-yield wafer output and potentially enables the seamless transition from lab-scale to industrial-scale 2D semiconductor complementary to silicon technology.

300 mm integration of a scalable phase change material spacer by inductively coupled plasma etching

To improve the heating efficiency and reduce the reset current of phase change memory, the volume-confined cells have been widely studied by employing highly conformal deposition techniques. In this work, a scalable confined structure with sidewall phase change material spacer is investigated for the integration in 12-inch wafer using physical vapor deposition and the subsequent anisotropic plasma etching back process. The finite element simulations reveal a remarkable 80% increase in heating efficiency by taking the confined structure. The isolated and compact trenches with the aspect ratio ranging from 0.40 to 1.04 are designed to accommodate the sidewall phase change material. The scaling down of the critical dimension of the rail-like spacer is observed as the aspect ratio increases. The spacer width of around 34 nm is well beyond the lithography capability used in this study. These results provide a promising path to fabricate the low-power and high-density memory device in a way fully compatible with the manufacturing technology.

An innovative application of double slider-crank mechanism in efficient of the scanning acoustic microscopy system

This paper proposes an innovative application of double slider-crank mechanism, which is utilized to develop a fast scanning module (FSM) of the scanning acoustic microscopy (SAM) system for evaluating the quality of 12-inch silicon wafer, that is, WFSAM system. In this application, the slider displacement and velocity are two critical parameters that must be carefully calculated to ensure the WFSAM system operates properly. Based on the scanning requirements, the slider displacement and velocity were calculated to determine the operation parameters of WFSAM system. A custom sample with known dimensions was prepared to scan using WFSAM system, which validated the WFSAM capabilities in order to provide internal information with accurate measurement. The quality of two 12-inch silicon wafers was evaluated using the WFSAM system. Finally, the design process of slider-crank mechanism is illustrated by a flowchart, which is used to develop the FSM of SAM system for inspecting any sample size.

Wafer Eccentricity Deviation Measurement Method Based on Line-Scanning Chromatic Confocal 3D Profiler

The wafer eccentricity deviation caused by misalignment between the center of the wafer and rotary table will lead to edge image distortion and quality degradation of the defect signals during automated inspection. However, wafer end jump and edge topography change will bring great challenges to the accurate measurement of micrometer deviations. A new wafer eccentricity deviation measurement method based on line-scanning chromatic confocal sensors (LSCCSs) is proposed. Firstly, the LSCCS with Z-axis submicron resolution used in the experiment acquires the 3D profile height of the wafer edge as the turntable rotates, and the edge distance is calculated at each rotation angle. Secondly, a robust Fourier-LAR fitting method is used to fit edge distance serial to reduce sensitivity to outliers. Finally, the wafer eccentricity deviation that is equal to the wafer center coordinate can be calculated using the wafer eccentricity deviation model. In the simulated experiment, the results show that the eccentricity deviation measurement accuracy was insensitivity to noise and reached the micron level. Additionally, the measurement uncertainty of eccentricity deviation coordinate Xw,Yw was (0.53 µm, 1.4 µm) in the actual data of the 12-inch wafers.

Nanoscale Phase Change Material Array by Sub-Resolution Assist Feature for Storage Class Memory Application

High density phase change memory array requires both minimized critical dimension (CD) and maximized process window for the phase change material layer. High in-wafer uniformity of the nanoscale patterning of chalcogenides material is challenging given the optical proximity effect (OPE) in the lithography process and the micro-loading effect in the etching process. In this study, we demonstrate an approach to fabricate high density phase change material arrays with half-pitch down to around 70 nm by the co-optimization of lithography and plasma etching process. The focused-energy matrix was performed to improve the pattern process window of phase change material on a 12-inch wafer. A variety of patternings from an isolated line to a dense pitch line were investigated using immersion lithography system. The collapse of the edge line is observed due to the OPE induced shrinkage in linewidth, which is deteriorative as the patterning density increases. The sub-resolution assist feature (SRAF) was placed to increase the width of the lines at both edges of each patterning by taking advantage of the optical interference between the main features and the assistant features. The survival of the line at the edges is confirmed with around a 70 nm half-pitch feature in various arrays. A uniform etching profile across the pitch line pattern of phase change material was demonstrated in which the micro-loading effect and the plasma etching damage were significantly suppressed by co-optimizing the etching parameters. The results pave the way to achieve high density device arrays with improved uniformity and reliability for mass storage applications.

마이크로웨이브 캐비티 모드 전환에 의한 웨이퍼 가열 특성

As a solution to the limitations of semiconductor miniaturization and multilayer technology, Atomic Layer Deposition(ALD) and Atomic Layer Etching(ALE) technologies are attracting attentions. For ALD and ALE process technologies, temperature uniformity is an important factor in determining the film quality of thin films and aspect ratio. Conventionally, an indirect heating method by a buried heater that heats the substrate is used, but the method has a decrease in productivity due to the preheating process. This study introduce a direct wafer heating method using GHz band microwaves to suggest the direction for new heater equipment to solve the problems of the existing method. At atmospheric pressure, the 2.45 GHz microwave is radiated through a double-slot antenna to heat a 12inch silicon wafer. The microwave propagates through the waveguide in TE10 mode and heats the wafer by cavity heating. It was confirmed through simulations and experiments that the wafer can be heated quickly using microwaves and the temperature distribution can be made uniform by the cavity conversion.

A Study on the Gap-Fill Process Deposited by the Deposition/Etch/Deposition Method in the Space-Divided PE-ALD System

This study concerns the development of a gap-fill process technology for isolating trench patterns. There are various gap-filling techniques in the case of trench patterns; nevertheless, a processing technology adopting the DED (deposition/etch/deposition) method was developed in this study. After the etch step, an Ar/O2 (1:2) plasma treatment technology reduced the residual amount of F in the films to 0.05%. By improving the etch uniformity, the deposition uniformity after the DED process on a 12-inch flat wafer was secured within <1%, and a high-quality SiO2 thin film with a dielectric constant of 3.97 and a breakdown field of 11.41 MV/cm was fabricated. The DED method can be used for gap-filling even in patterns with a high aspect ratio by changing process parameters, such as RF power and division of etch steps, according to the shape, depth, and CD size of the pattern. This study confirmed that a void-free gap-fill process can be developed in a trench pattern with a maximum aspect ratio of 40:1.

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A novel circle center location method for a large-scale wafer

The high-precision circle center location of a wafer can implement the automatic acquisition of the special die, which is one of the most significant steps in wafer surface defect detection. Due to the larger scale of the wafer and the smaller field of view of the camera, the circular arc edge captured is an approximate line segment and has less arc information. The existing methods are mainly used to locate the circle center of the full or more than half of the circular arc captured by a large field of view camera, and it is extremely difficult to accurately locate the circle center of the wafer. To solve this problem, we propose a novel circle center location method for the large-scale wafer. A method for measuring the system angle in the horizontal plane by calibration is presented. Throughthe analysis of multiple error sources and the compensation of systemangle, the system angle inthe horizontal plane is the main source of error that causes the positioningerror of the inspection system. Based on the distance constraint and the system angle compensation in the horizontal plane, the edge point set coordinates of multi-segment circular arc images are accurately extracted and transformed in the reference coordinate system. A new hierarchical Bayesian model, which takes the initial circle parameter obtained by an improved method as a priori constraint, is utilized to accurately estimate the circle center and radius of the wafer. The effectiveness of the proposed method is verified by various experiments, which are conducted with real 8-inch and 12-inch wafers using the inspection equipment developed.

Metasurface-based subtractive color filter fabricated on a 12-inch glass wafer using a CMOS platform

Optical color filters are widely applied in many areas including display, imaging, sensing, holography, energy harvest, and measurement. Traditional dye-based color filters have drawbacks such as environmental hazards and instability under high temperature and ultraviolet radiation. With advances in nanotechnology, structural color filters, which are based on the interaction of light with designed nanostructures, are able to overcome the drawbacks. Also, it is possible to fabricate structural color filters using standard complementary metal-oxide-semiconductor (CMOS) fabrication facilities with low cost and high volume. In this work, metasurface-based subtractive color filters (SCFs) are demonstrated on 12-inch (300-mm) glass wafers using a CMOS-compatible fabrication process. In order to make the transmissive-type SCF on a transparent glass wafer, an in-house developed layer transfer process is used to solve the glass wafer handling issue in fabrication tools. Three different heights of embedded silicon nanopillars (110, 170, and 230 nm) are found to support magnetic dipole resonances. With pillar height and pitch variation, SCFs with different displayed colors are achieved. Based on the resonance wavelength, the displayed color of the metasurface is verified within the red-yellow-blue color wheel. The simulation and measurement results are compared and discussed. The work provides an alternative design for high efficiency color filters on a CMOS-compatible platform, and paves the way towards mass-producible large-area metasurfaces.

Combining an automatic material handling system with lean production to improve outgoing quality assurance in a semiconductor foundry

This research uses a case study methodology to investigate ways of improving the outgoing quality assurance (OQA) processes of a 12-inch wafer foundry. It applies the value stream mapping method of lean production to analyse the wafer OQA processes. The study ensures that all outgoing wafers satisfy customers’ requirements without waste. In this paper, a current state map is used to locate potential waste and problematic process flows. Meanwhile, system simulation is adopted to construct the automatic material handling system and the equipment, transportation, and dispatching automation production module for the OQA processes—namely, the To-Be model and the future state map. The empirical results show that, for the To-Be model, the total lots of three customers per month increased from 3,106 to 3,719 pieces—about a 20% increase—and that the average product cycle time for customers A, B, and C dropped by 43.67%, 57.91%, and 58.39%, respectively. Furthermore, the operators’ utilisation rate increased from 61% of 10 operators on the day and night shifts to 87.26% of seven operators on the day and night shifts—about a 30% decrease of labour costs. Therefore, this study applies lean production (removing the non-value-added activities) and automation to improve the case company’s wafer OQA processes.

CMOS-compatible a-Si metalenses on a 12-inch glass wafer for fingerprint imaging

Abstract Metalenses made of artificial sub-wavelength nanostructures have shown the capability of light focusing and imaging with a miniaturized size. Here, we report the demonstration of mass-producible amorphous silicon metalenses on a 12-inch glass wafer via the complementary metal-oxide-semiconductor compatible process. The measured numerical aperture of the fabricated metalens is 0.496 with a focusing spot size of 1.26 μm at the wavelength of 940 nm. The metalens is applied in an imaging system to test the imaging resolution. The minimum bar of the resolution chart with a width of 2.19 μm is clearly observed. Furthermore, the same system demonstrates the imaging of a fingerprint, and proofs the concept of using metalens array to reduce the system size for future compact consumer electronics.

Business ecosystem and technology roadmap for Taiwan’s TFT-LCD industry

ABSTRACT During the past two decades, Taiwan, a reliable source of quality 12-inch wafer manufacturing, grew to become the largest supplier of TFT-LCD panels in the world. The financial crisis in 2008 and increasing competition from other Asian manufacturers shortly after, led to the current scenario, which is characterised by global oversupply, demand fluctuations and price volatility. As a result, several Taiwan’s TFT-LCD manufacturers attempted to break through these difficulties. This paper proposes the technology roadmap for Taiwan’s TFT-LCD and describes three methods to analyse the current strengths, limitations and future potential of the suggested technology roadmap: Dynamic Five Forces framework, Business Ecosystem and Industry Value Chain. The results suggest that developing a business ecosystem lifecycle could obtain an appropriate technology roadmap for Taiwan’s TFT-LCD industry. The study provides useful observations and directions for management and business coalitions involved in drafting and executing globally competitive strategies.

Large-area pixelated metasurface beam deflector on a 12-inch glass wafer for random point generation

Abstract Metasurface-based beam deflector, as an important optical element to bend the light propagation direction, has drawn a lot of interests in research to achieve miniaturization of devices and reduction of system complexity. Based on the 12-inch immersion lithography technology, in this work, an ultra-thin and large-area pixelated metasurface beam deflector with a footprint of 2500 × 2500 μm, formed by nanopillars with diameters from 221 to 396 nm, is demonstrated on a 12-inch glass wafer. The 21 × 21 array of deflectors is designed to bend the input light in different directions and to generate 441 random points. In addition, the layer transfer on the 12-inch glass wafer makes the device working in transmission mode at a 940-nm wavelength. The random point array generated from the experiment shows good match with the design. This pixelated metasurface beam deflector can generate random points simultaneously and has potential to make beam steering by switching each pixel of the beam deflector, which can be applied on motion detection, facial recognition, and light detection and ranging.

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

The formation of various deep silicon structures using plasma etching has wide applications in sensors, micro-electro-mechanical systems and 3D wafer level integration. However, the fabrication of silicon cavities with high accuracy at depth within a large wafer size is still a challenge due to the large amount of etching required. Herein, silicon cavity etching uniformity approaching 3% in a depth of ~100 µm on a 12-inch wafer is achieved through tuning the focus ring height, baffle shape, double zone helium cooling system and chamber pressure. The simulation of the electromagnetic field and gas flow field separately provides the guidance for the improvement, and the way in which the wafer temperature influences the etch uniformity is demonstrated. These results have significance for both the understanding of the plasma etching mechanism and the practical application of the silicon etching process for advanced device fabrication.

CMOS-compatible all-Si metasurface polarizing bandpass filters on 12-inch wafers.

The implementation of polarization controlling components enables additional functionalities of short-wave infrared (SWIR) imagers. The high-performance and mass-producible polarization controller based on Si metasurface is in high demand for the next-generation SWIR imaging system. In this work, we report the first demonstration of all-Si metasurface based polarizing bandpass filters (PBFs) on 12-inch wafers. The PBF achieves a polarization extinction ratio of above 10 dB in power within the passbands. Using the complementary metal-oxide-semiconductor (CMOS) compatible 193nm ArF deep ultra-violet (DUV) immersion lithography and inductively coupled plasma (ICP) etch processing line, a device yield of 82% is achieved.

Optimum design of a large area, flexure based XYθ mask alignment stage for a 12-inch wafer using grey relation analysis

Abstract An optimum design methodology for a large area, flexure-based XYθ mask alignment stage, which can be applied to a 12-inch wafer photolithography process, was presented. The XYθ micropositioning stage consisted of a working plate with a 12-inch hole in the center, three piezo actuators, and three displacement amplifiers based on the bridge-type flexure mechanism. Grey relation analysis and orthogonal array were incorporated with finite element analysis to find optimum design conditions. The grey relation grade with weight factors was used to simultaneously optimize three objective characteristics of the micropositioning stage: the maximum stroke, deflection of the working plate, and first natural frequency. The optimally-designed stage was fabricated by wire electrical discharge machining and tested to investigate its performance. The proposed stage showed the first natural frequency of 57 Hz and the maximum stroke of 122.84 μm, 108.46 μm, 0.685 mrad in the x-, y-, and θ-direction, respectively. The resolutions in corresponding directions were 11 nm, 10 nm, and 0.5 μrad. The performance of the stage was improved by optimum design process, and the experimental results were in good agreement with the predicted ones from the finite element analysis.