50nm Gate Length Research Articles

Enhancing the noise performance of monolithic microwave integrated circuit-based low noise amplifiers through the use of a discrete preamplifying transistor

An approach to enhancing the noise performance of an InP monolithic microwave integrated circuit (MMIC)-based low noise amplifiers (LNA) through the use of a discrete 100-nm gate length InP high electron mobility transistor is outlined. This LNA, known as a transistor in front of MMIC (T + MMIC) LNA, possesses a gain in excess of 40 dB and an average noise temperature of 9.4 K across the band 27 to 33 GHz at a physical temperature of 8 K. This compares favorably with 14.5 K for an LNA containing an equivalent MMIC. A simple advanced design system model offering further insights into the operation of the LNA is also presented and the LNA is compared with the current state-of-the-art Planck LFI LNAs.

Novel Design Methodology Using <formula formulatype="inline"><tex Notation="TeX">$L_{\bf EXT}$</tex></formula> Sizing in Nanowire CMOS Logic

In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive matching issue in NW/FinFET based CMOS circuits. We show that, in comparison to conventional CMOS, where the number of NWs/fins in p-FET is used to match n-FET drive, the proposed approach provides a significant reduction in circuit active area and power dissipation. When compared to conventional CMOS inverter, the proposed approach shows 20% lower area, and 35% saving in power in case of NW CMOS inverter. Our results show that extension length tuned-CMOS has an excellent option for low-power applications in both NW and FinFET technologies.

Microwave Analysis for Intrinsic and Extrinsic Characteristics of AlGaN/GaN pHEMT

In this paper, a simple non-linear analytical charge control model for the DC and microwave characteristics of AlGaN/GaN MODFET is presented. The effect of parasitic resistances R is also incorporated. The model has also been extended to obtain the expressions for transconductance, drain conductance and cut-off frequency of the device. The model predicts a high transconductance of 502.6mA/mm at 1Vof gate bias and a maximum cut-off frequency of 22.5GHz for a 50nm device gate length, which is important in realizing the device for microwave applications. The extrinsic and intrinsic characteristics show close agreement with the published results proving the validity of the model.

An ultra clean self-aligned process for high maximum oscillation frequency graphene transistors

Owing to its ultra high carrier mobility, graphene transistor shows great application potential as high-frequency electronics. Intrinsic cutoff frequency (fT) of 427GHz has been reported. But the maximum oscillation frequency (fmax) remains low, limiting its use in practical radio-frequency (RF) circuits. Here, we report an ultra clean self-aligned graphene transistors fabrication by pre-deposition of gold film on graphene as protection layer. This improved self-aligned fabrication keeps graphene away from any possible contamination, which makes our graphene transistors show good gate coupling and less parasitics, thus good dc and RF performances. The 100nm gate-length graphene transistor exhibits a fmax of 105GHz. Our study shows a pathway to fabrication of high-performance graphene transistors for future application in RF circuits.

A Conjoined Electron and Thermal Transport Study of Thermal Degradation Induced During Normal Operation of Multigate Transistors

A 3-D full-band particle Monte Carlo (MC) simulator, with full electron and phonon dispersion and a 2-D quantum correction is self-consistently coupled to a phonon MC simulator. The coupling entails feeding the phonon data obtained from the 3-D electrical MC to the phonon MC. The phonon MC reciprocates by providing the resulting spatial temperature map, which is used in the electron MC, with temperature-dependent scattering table, in a self-consistent manner. A key feature of our model is its ability to delineate the influence of the various phonon modes on the electronic transport through the application of anharmonic phonon decay and full phonon dispersion. The electrothermal simulator developed is utilized to assess the performance of silicon-on-insulator (SoI) multigate (MG) MOSFET with nanoscale cross sections. This paper shows that the hotspot in inversion mode SoI MG MOSFET with 20-nm gate length permeates into the channel as the cross section is reduced (covering ~ 50% of the channel for the 5 nm × 5 nm cross section). Furthermore, cross-sectional scaling, a key design rule to mitigate short-channel effects, degenerates device performance well beyond the ideal current gain limits of MG MOSFET architecture of double-gate, trigate, and gate-all-around MOSFET. Consequently, at the sub-20-nm scale adding more gate does not necessarily improve performance.

A $W$-Band Monolithic Integrated Active Hot and Cold Noise Source

For application in radiometry or noise measurement systems, an integrated active hot-cold load (AHCL) operating in the W-band (75-110 GHz) is presented and realized as monolithic millimeter-wave integrated circuit (MMIC). It makes use of a novel circuit topology that employs only a single active noise source and monolithic integrated switches to provide a cold and a hot noise reference temperature. The AHCL provides a measured cold temperature of only 230 K and a hot temperature of 860 K around 94 GHz, thus enabling two-point radiometric calibration and absolute power measurements. The noise source of the AHCL has been fabricated as a two-port test structure too. In that configuration, it has been measured as a low-noise amplifier with a noise figure of 2.5 dB at 94 GHz proving its good noise performance. As a standalone active cold load (ACL), an excellent noise power of only 190 K at 93 GHz is achieved. The AHCL and ACL MMICs have been fabricated in 100-nm gate-length metamorphic high electron-mobility transistor technology.

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT=2 nm) and dielectric, HfO2 at VGS=1 V and temperature of 300 K have ION of 0.02-12.5 mA/μm, ION/IOFF of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> , and subthreshold swing (average) of 16-74 mV/decade.

100-nm T-gate InAlAs/InGaAs InP-based HEMTs with fT = 249 GHz and fmax = 415 GHz

InAlAs/InGaAs high electron mobility transistors (HEMTs) on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency fmax are reported. An InAlAs/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain—gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 OM·mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InAlAs/InGaAs InP-based HEMTs. The outstanding gm.max fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.

Investigation of the random dopant fluctuations in 20-nm bulk MOSFETs and silicon-on-insulator FinFETs by ion implantation Monte Carlo simulation

In this paper, we proposed a simulation approach for studying the random dopant fluctuation (RDF) effects in the nanoscale MOSFETs using only the TCAD tools. We use this approach to simulate the RDF effects in the 20-nm gate-length bulk MOSFETs, silicon-on-insulator (SOI) single-gate (SG) and triple-gate (TG) FinFETs for demonstration. This approach utilises the stochastic nature of the Monte Carlo (MC) simulation of ion implantation to capture the RDF phenomena in the devices. The simulation results show that the standard deviation of the threshold voltage ( σV T ) is approximately proportional to the cube root of the channel doping concentration for the simulated conventional bulk MOSFETs. For the SOI SG and TG FinFETs, the σV T increases much less than that of the conventional bulk MOSFETs as the channel doping concentration increases. Besides, the σ V T of the SOI TG FinFETs show about 30–40% reductions comparing to those of the SOI SG FinFETs. The average of the MC simulation results agrees with the implant table simulation results. The reasonable simulation results verify the validity of this TCAD simulation scheme for the RDF study.

Under-the-Barrier Model: An Extension of the Top-of-the-Barrier Model to Efficiently and Accurately Simulate Ultrascaled Nanowire Transistors

In this paper, we present a computationally efficient full-band method to determine the current characteristics of circular, gate-all-around nanowire (NW) FETs in the sub-10-nm regime. The well-established top-of-the-barrier model is extended to consider intraband tunneling through the Wentzel-Kramers-Brillouin approximation. The required electrostatic potential is obtained using a parabolic approximation for its radial component, thus reducing Poisson equation to an 1-D problem and the computational burden by several orders of magnitude. After validating the model with 3-D, full-band, atomistic quantum transport simulations, the properties of Si, Ge, and InAs NW FETs are studied as function of their diameter and gate length. It is found that below 10-nm gate lengths Si NW transistors outperform Ge , independently from their diameter. On the other hand, InAs wires with diameters below 6 nm exhibit higher ON-currents than their Si counterparts.

Junctionless Tunnel Field Effect Transistor

In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high-k dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio (~6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), a point subthreshold slope (SS) of ~38 mV/decade, and an average SS of ~70 mV/decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.

Optimization of SiC:P Raised Source Drain Epitaxy for Planar 20nm Fully Depleted SOI MOSFET Structures

This paper will focus on the capability of a low-temperature cyclical deposition/etch (CDE) epitaxy process based on Si2H6 to fabricate SiCP films exhibiting very-high, electrically-active P and C concentrations with fast growth rates. This process will be characterized on blanket wafers first and optimized for raised source/drain applications in planar FDSOI technology featuring 20nm design rules. Low temperature drive-in anneal in combination with high phosphorus doping was employed leading to best resistivity values of 0.3 mΩ.cm for SiP and 0.6 mΩ.cm for SiC2%P. We will show that increasing the phosphorus concentration in the layers enables us to have the same transistor overlap after diffusion anneal for comparable resistivity with SiP films and improved carbon substitutionality. Best Ron values as low as 220Ω.μm will be reported, measured on 20nm gate length transistors in planar FDSOI technology with an optimized process.

Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors

Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current (Ion), off-state leakage current (Ioff), and subthreshold swing is examined by means of statistical technology computer-aided design simulations with consideration of body LER up to 1 nm in amplitude as well as RDF for body heights ranging from 10 to 40 nm. The effects of body LER and RDF are found to be similar in magnitude and also comparable to those in similarly designed fin FETs, with the exception of Ion variability which is roughly three times higher for TFETs. Arguments are presented to explain these findings based on the operating principle of TFETs compared to standard metal-oxide-semiconductor-FET-based technology.

Simulation of DC Characteristics of Nano-Scale Hydrogen-Terminated Diamond MISFETs

ABSTRACTAn improved 2D device model is generated to simulate the DC properties of hydrogen- terminated diamond MISFETs by taking into account the effect of electric field on hole mobility. At high lateral field, the mobility degrades due to velocity saturation and at high transverse field, the mobility decreases because of strong surface phonon scattering. As either field increases to a certain level (∼ 1MV/cm), the mobility becomes independent of doping concentration and the maximum transverse field appears at the boundary between surface acceptor region and bulk. The threshold voltage is found to be a strong function of gate length and can change from negative to positive, which will change the operation mode of the device. In addition, the simulation also shows that the transconductance reaches a maximum value at 80nm gate length but decreases after further shrinkage, which might be also related to the velocity saturation effect induced by large lateral field.

Design of Double Delta-Doped Al&lt;sub&gt;0.22&lt;/sub&gt;Ga&lt;sub&gt;0.78&lt;/sub&gt;As/In&lt;sub&gt;0.22&lt;/sub&gt;Ga &lt;sub&gt;0.78&lt;/sub&gt;As Pseudomorphic HEMTs

In this study, performances of double delta-doped AlGaAs/InGaAspseudomorphic high electron mobility transistors are investigated. Simulation results demonstrate good performance for this structure. Form simulation, the structure demonstrates a maximum current gain cutoff frequency of 145GHz for 100nm gate length, a peak extrinsic transconductance of 526mS/mm, and a maximum saturation current density of 350mA/mm.

Hydrogen-Terminated Diamond Field-Effect Transistors With Cutoff Frequency of 53 GHz

Homoepitaxial diamond has been used to demonstrate the RF performance of 50-nm gate length hydrogen-terminated diamond field-effect transistors. An extrinsic cutoff frequency of 53 GHz is achieved which we believe to be the highest value reported for a diamond-based transistor. The generation of an RF small signal equivalent circuit is used to extract device elements to better understand variation between intrinsic and extrinsic operation. An intrinsic cutoff frequency of 90 GHz is extracted through this process, verifying the requirement to minimize access resistance to maximize the potential high-frequency performance of this technology.

Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate

We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 103/2.9 × 103 μA/μm at |VD| = |VG - Vt| = 1.0 V, Ion/Ioff ratio as high as 5 × 108/109, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.

One-flux theory of saturated drain current in nanoscale transistors

We present an expression for the saturated drain current in nanoscale transistors based on multiple reflections of carriers at the virtual source from two adjacent scattering “black boxes”. Under certain assumptions and simplifications this new expression reduces to the well known Lundstrom’s formula and also to the recent model by Giusi et al. Six macroscopic parameters appear in the ‘exact’ form of this model. We do not discuss how to derive physical expressions for these parameters. Rather, we emphasize the limitations of Lundstrom’s model when applied to nanoscale transistors. Some existing formulae for the carrier backscattering coefficient are examined and compared to our results. We verify our model through a consistency test based on simulation data of a 10nm gate-length silicon nanowire transistor.

Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering

In this paper, we develop a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of Schottky barrier MOSFETs (SB-MOSFETs). We have checked it reproducing experimental results of 20-nm gate-length SB-MOSFETs with NiSi and epitaxial NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S/D contacts. We make use of the Wentzel-Kramers-Brillouin (WKB) approximation to get the tunneling probabilities through the lowered barriers along with an appropriate calibration of the effective masses which compensates to a large extent the lack of accuracy of the WKB model when diverting from the “wide barrier” assumption. A vertical discretization of the channel is also included to allow the barrier height dependence on the depth inside the channel. We show that corrected simulations including this effect describe in a very accurate way the behavior of these devices. We also check that the striking experimental observation of tunneling current reduction at very short gate lengths is also obtained, in contrast to the scaling behavior of conventional MOSFETs. We successfully explain this fact invoking the modification of the potential inside the channel, i.e., the overlapping of source and drain potential profiles leads to an increase of its total value even though BL mechanisms tend to decrease it in the vicinity of the contacts.

Fabrication of 100-nm Metamorphic AlInAs/GaInAs HEMTs Grown on Si Substrates by MOCVD

High-performance metamorphic Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.49</sub> In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.51</sub> As-/Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47-</sub> In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> As high-electron-mobility transistors (mHEMTs) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD) using an effective multistage composite buffer scheme have been fabricated. Room-temperature Hall measurements show an average sheet carrier density of 4.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> with a mobility of over 7500 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s. Maximum transconductance of mHEMTs with a 100-nm gate length was ~ 770 mS/mm, which is nearly the same as that of mHEMTs with the same dimension grown on GaAs substrates by MOCVD. The unity current gain cutoff frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> ) and the maximum oscillation frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) were 210 and 146 GHz, respectively. To our best knowledge, these results are the best reported for MOCVD-grown mHEMTs on Si.