1-tap DFE Research Articles

A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5~\mu \text{A}_{\mathrm {rms}}$ </tex-math></inline-formula> input-referred noise. Optical measurement results at 100 Gb/s show that −8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency.

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Low-Latency Burst Error Detection and Correction in Decision-Feedback Equalization

This article describes low latency, zero overhead DFE burst error correction technique. Without any encoder or decoder latency, the proposed technique makes use of the existing pre-cursor ISI to detect and correct errors on a burst of data. The implemented proof-of-concept 2-tap DFE prototype in 65nm CMOS operates at 16 Gb/s and compensates 32 dB loss consuming 58 mW only. With an additional 18 mW, the receiver enables error correction capability that translates to 2-to-6 dB SNR gain depending on the pre-cursor magnitude. Experimental results demonstrate that for lossy channels where pre-cursor is 60% or higher of main, this error correction outperforms RS(528, 514) without any overhead and with much lower latency and power consumption.

A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

A 19–27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19–27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm $^{2}$ only.

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3" FR4 microstrip line, and at 7 Gb/s with a 0.6" FR4.

A Blind Baud-Rate ADC-Based CDR

This paper proposes a 10-Gb/s blind baud-rate ADC-based CDR. The blind baud-rate operation is made possible by using a 2UI integrate-and-dump filter, which creates intentional ISI in adjacent bit periods. The blind samples are interpolated to recover center-of-the-eye samples for a speculative Mueller–Muller PD and a 2-tap DFE operation. A test chip, fabricated in 65-nm CMOS, implements a 10-Gb/s CDR with a measured high-frequency jitter tolerance of 0.19 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{UI}_{\rm PP}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm \hbox{300 ppm}$</tex></formula> of frequency offset.

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> RJ, 0.8 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> input sensitivity and a 0.7-UI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Maximum baud rate of electrical signaling over backplanes is limited by reflection and crosstalk noise at connectors as well as ISI caused by frequency-dependent dielectric loss. A DFE is an effective circuit to alleviate ISI without amplifying noise. A multi-tap DFE is often used in order to cancel long-tail ISI [1–3]. However, multiple DFE taps may limit maximum operation speed due to analog feedback when using non-speculative taps [1,2], or increase power and area exponentially when using multiple speculative taps [3]. Another approach is a combination of a 1-tap speculative DFE to get faster speed and a linear equalizer (LE) to cancel the long-tail ISI [4,5]. Adaptive control is challenging when combining LE and DFE, because the relationship between LE and DFE must be taken into account [5], and the sign-sign-least-mean-square (SS-LMS) algorithm [7] that is commonly used in DFEs is not applicable to some types of LE, or at the cost of increased power and area for parallel signal paths in LE [6]. The zero-forcing (ZF) algorithm for analog filters [8] is applicable to any type of LE, but it needs an ADC and a large amount of logic to perform matrix multiplication. A heuristic algorithm [5] requires an eye measurement circuit, microcontroller, and control software.