Abstract
This article describes low latency, zero overhead DFE burst error correction technique. Without any encoder or decoder latency, the proposed technique makes use of the existing pre-cursor ISI to detect and correct errors on a burst of data. The implemented proof-of-concept 2-tap DFE prototype in 65nm CMOS operates at 16 Gb/s and compensates 32 dB loss consuming 58 mW only. With an additional 18 mW, the receiver enables error correction capability that translates to 2-to-6 dB SNR gain depending on the pre-cursor magnitude. Experimental results demonstrate that for lossy channels where pre-cursor is 60% or higher of main, this error correction outperforms RS(528, 514) without any overhead and with much lower latency and power consumption.
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