2-tap Decision Feedback Equalizer Research Articles

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10^-12 with an eye width of 100 mUI with -7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.

A 1.68–23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant Unlimited Range Frequency Detector

This paper presents a reference-less half-rate receiver with an unlimited range frequency detector (URFD) for 13.8X continuous rate operation. To tolerate channel loss induced inter-symbol interference (ISI), the receiver is integrated with a continuous time linear equalizer (CTLE) and a 2-Tap decision feedback equalizer (DFE) on the same chip. Incorporating with the novel pulse width based URFD, the date rate of the receiver is limited by the frequency tuning range of the voltage-controlled oscillator (VCO). The energy efficiencies of the whole receiver and clock data recovery (CDR) are about 2.39 and 0.97 pJ/bit respectively. Implemented in a TSMC 28-nm CMOS process, the active area is 0.056 mm.

112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels

A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel’s 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, −35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.

An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss

This brief presents a channel-included filtering feed-forward equalizer (FFE) scheme suitable for data transmission through a heavily-dispersive lossy channel. The proposed scheme adjusts the tap weights so that the impulse response seen at the receiver has only a 2-unit interval (UI)-long impulse response with other parts negligible. The confinement of each bit response to a 2-UI period effectively achieves a lossless duobinary-like eye opening and enables data recovery with only a 1-tap decision-feedback equalizer (DFE). The proposed transceiver, implemented in 28-nm LP CMOS technology, achieved data recovery of 18 Gb/s up to 32-dB loss with only 3-tap FFE at the transmitter and 1-tap DFE at the receiver.

A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS

This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback equalizer (DFE) fabricated in 28-nm CMOS. The proposed on-chip adaptation engine is tailored to a baud-rate CDR, where the front-end comparators are shared between the DFE and the PD to save power. The adaptive scheme is demonstrated on a baud-rate CDR testchip that has sampler-based front-end equalization which is more suitable for low-power, short reach, applications instead of a power intensive ADC/DSP-based receiver approach that is usually meant for long-reach (LR) links. This testchip was validated with 34–36 Gb/s random input data (PRBS31 & 7) with channel loss of 15.05–18.25 dB at Nyquist. The total power consumption is measured to be 106.3 mW, equivalent to an FOM of 3.04 pJ/bit at 35 Gb/s.

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces

In asymmetric memory systems, the pull-up and pull-down data from the channel can have different amounts of inter-symbol interference (ISI), so they cannot be fully corrected by an equalizer which uses a single tap weight. We introduce a receiver-side single-ended 1-tap asymmetric decision-feedback equalizer (DFE) with a weight selection multiplexer, which allows the application of a different weight to each direction of data value transition. Implemented in a 55-nm CMOS technology, our DFE compensated for asymmetric ISI in a 10.4-Gb/s signal from a channel with an insertion loss of −8.3 dB, leading to a 50% wider horizontal margin at a bit-error-rate of 10−12 than symmetric correction. The energy efficiency is 0.16 pJ/bit.

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> when operated with a 2-tap FFE transmitter.

A 26-Gb/s 0.31-pJ/bit Receiver With Linear Sampling Phase Detector for Data and Edge Equalization

A source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) using an embedded feed forward equalizer (FFE) and decision feedback equalizer (DFE) is proposed for chip-to-chip/module-to-module communication with medium channel loss. The quarter-rate LSPD is proposed to save power and avoid dithering jitter in a nonlinear bang-bang phase detector. To relax the timing constraint and improve the jitter performance of the recovered clock, a 1-tap FFE and a 1-tap DFE are applied to both the data path and the edge path so as to cancel the first and second post-cursors by reusing the linear samples. A charge-steering technique is adopted in the equalizer summer to minimize the power overhead. The receiver IC is fabricated in a 28-nm CMOS process and achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/b while tolerating a 14-dB channel loss at 13 GHz.

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output to increase the time opening. The time comparator makes a decision with the first arriving edge of the two outputs of the TB DFE. While the feedback loop delay must be less than 1 UI for proper operation in the conventional voltage-based DFE, the TB DFE allows the feedback loop delay up to 1.43 UI in this paper. A transmitter (TX) transmits a single-ended signal of 200-mV swing by using an n-over-n voltage-mode driver. The transceiver in a 65-nm CMOS process achieves a 12.5 Gb/s with a 0.8-V supply through a 15-inch FR-4 channel of 14-dB loss. The TX and RX chip consume 4.3 and 3.4 mA, respectively. The energy efficiency is 0.49 pJ/b.

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid analog and digital equalizations. The analog equalization is performed using two identical stages of continuous time linear equalizer, each having a constant of ~0-dB dc-gain and a maximum peaking of ~7 dB peaking at 14 GHz. A 28-GSample/s 32-way time-interleaved SAR ADC converts the equalized analog signal into digital domain for further equalization using digital signal processing. The transceiver achieves <;1e-8 bit error rate over a backplane channel with 31-dB loss at 14-GHz and 3.5-mVrms additional crosstalk, using a fixed ~10-dB TX equalization and an adaptive hybrid RX equalization, with the DSP configured to have a 24-tap feed forward equalizer and a 1-tap decision feedback equalizer. The transceiver consumes 550-mW power at 56 Gb/s, excluding the power of the on-chip configurable DSP that cannot be accurately measured as it is implemented as part of a larger test structure.

A 3.12 pJ/bit, 19–27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

A 19–27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19–27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm $^{2}$ only.

A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE

A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a pre-cursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15-22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm × 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm × 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer

A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm2, respectively.

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link

This paper introduces a novel signaling scheme for parallel high-speed interfaces. The new signaling, called coded differential (CD), maps two bits of information to four wires and, therefore, has the same pin-efficiency as differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. The CD receiver also incorporates differential detection with no need for a dc reference. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, CD leads to substantial increase in timing margin compared with a differential link with 1-tap decision feedback equalizer (DFE). Unlike DFE, CD does not require channel tap estimation. The theory of CD signaling, the optimization of the encoder and the decoder, and the implementation details of a prototype system developed based on this scheme for graphics memory interfaces are described. The full-featured interface, implemented in a 40-nm CMOS process, transfers 8 × 16 Gb/s data over 16 wires and achieves an energy efficiency of 4.1 pJ/b. Eye diagram measurements on a scope indicate 30% improvement in timing margin compared with a 1-tap predictive DFE system.

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5″ NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps.

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

The design and experimental results of a low-power, low-area 5-tap decision feedback equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported. The DFE employs a low-power current-integrating summer with sampling front-end, which eliminates systematic frequency-dependent loss inherent in conventional integrating serial receivers. Further power and area savings are achieved through the use of a direct-feedback architecture and CMOS-style rail-to-rail clocking. The 5-tap DFE core occupies 73 times 50 mum2 and consumes 11 mW from a 1 V supply when equalizing 12 Gb/s data passed over a 30 channel with 15 dB of loss at 6 GHz.