1-bit Full Adder Cell Research Articles

Statement of Removal: Design and analysis of 1-bit hybrid full adder cells for fast computation

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.

Design and analysis of 1-bit hybrid full adder cells for fast computation

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.

FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA

A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

A Novel Design of Full Adder Cell for VLSI Applications

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high–performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy delay product (EDP) are extracted and compared for proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value 1.377 µW and the NMNFA exhibits highest value 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages proposed adder deliver low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At supply voltage 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported adder MBFA in this paper.

Design and implementation of ternary adder for High-Performance arithmetic applications by using CNTFET material

This work presents 1-bit hybrid full adder cell using proposed ternary logic along with carbon nanotube. The novelty of this design is the remarkable optimization of power consumption by reducing the hardware part which makes it area efficient and low power. Wide bandwidth and High speed are other salient features of the presented design. To begin with Proposed ternary logic, it works in three logic level in addition to that it improvises dynamic performance of full adder along with CNT technology to maintain the law of scalability for enhancing the silicon technology. The work has been simulated on HSPICE software using 32 nm process CNTFET technology. The operation voltage was.9V at 100 MHz frequency. The relative improved percentage in the area and PDP to be found 13.01–56.18% and 14.27–58.54% respectively. In order to provide fair comparison relative data of similar studies and simulated results has been carried out and put in the tabular form in the later part of the paper.

LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS

In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72% improvement). The proposed cell simulated in HSPICE with 32nm CMOS technology in four different scenarios. First, the proposed cell was assessed as a 1-bit full adder cell; second, the proposed cell applied in a 4-bit carry ripple adder structure. In the third and fourth scenarios, the proposed cell's power consumption and performance were assessed in different power supply voltages, temperatures, and a larger load capacitor. Approximate computing is a design paradigm that is applicable in image processing as an error-resilient application. MATLAB exploited to assess the proposed approximate full adder in image addition application in three different scenarios. The outputs evaluated by different image quality metrics (such as peak signal to noise ratio (PSNR)) and the final outputs of approximation are acceptable in this application due to image quality metrics.

Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems

In this paper, we present two novel approximate Full Adder cells with capacitive threshold logic (CTL) using carbon nanotube field-effect transistor (CNFET) technology. To investigate the efficiency of the proposed cells, extensive simulations are carried out at both application and transistor levels. At the application level, by using the MATLAB tool, the proposed cells are applied to the motion detector algorithm as one of the practical image processing applications. Peak signal-to-noise ratio (PSNR) is considered as a legitimate application-level evaluating factor. In addition, by using the HSPICE tool, the hardware level parameters such as average power consumption, delay, and power-delay product (PDP) are estimated. Then, a compromise between the application and hardware-level metrics is considered. Noise analysis is also accomplished by taking noise immunity curve (NIC) and average noise threshold energy (ANTE) into account. Furthermore, Monte Carlo transient analysis is exploited to study the robustness of the introduced cells against diameter deviations of the carbon nanotubes (CNTs). Simulation results indicate the supremacy of the proposed cells compared to others.

Energy Efficient GDI Based Full Adders For Computing Applications

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

Design and analysis of different full adder cells using new technologies

<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications

ABSTRACTCarbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary full adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based full adder, and are compared to the other adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary full adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81% and 80%, respectively, improvement in power consumption and PDP.

An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

ABSTRACTThe design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.

Design and software characterization of finFET based full adders

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

Implementation Topology of Full Adder Cells

Abstract Design of different complementary metal-oxide-semiconductor (CMOS) topologies of 1-bit full adder (FA) cell in terms of power, delay, power-delay-product (PDP) and energy-delay-product (EDP) have been analyzed for the application of the intelligent systems. The FA cells have been implemented with respect to the different CMOS topologies such as complementary-CMOS (C-CMOS), complementary pass-transistor logic (CPL), CMOS transmission gates (TGA), and CMOS transmission function (TFA) and simulated at 180 nm technology. The work has been extended to the comparison of FA cell implementation using the increasingly demanding ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Based on the simulation results, the application of UTBSOI in the FA cell has resulted in 26.7%, 24.3%, 44.6% and 44.7% improvements over that of best design architecture reported in this literature in terms of power, delay, PDP, and EDP, respectively.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

ABSTRACTThis paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.

Low-power, high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing

ABSTRACTIn this paper, three novel low-power and high-speed 1-bit inexact Full Adder cell designs are presented based on current mode logic in 32 nm carbon nanotube field effect transistor technology for the first time. The circuit-level figures of merits, i.e. power, delay and power-delay product as well as application-level metric such as error distance, are considered to assess the efficiency of the proposed cells over their counterparts. The effect of voltage scaling and temperature variation on the proposed cells is studied using HSPICE tool. Moreover, using MATLAB tool, the peak signal to noise ratio of the proposed cells is evaluated in an image-processing application referred to as motion detector. Simulation results confirm the efficiency of the proposed cells.