Abstract
As an implementation of the static random access memory (SRAM), the tunnelling SRAM (TSRAM) uses the negative differential resistance of resonant (interband) tunnelling diodes (R(I)TDs) and potentially offers improved standby power dissipation and integration density compared with the conventional CMOS SRAM. TSRAM has not yet been realised with a useful bit capacity mainly because the level of reproducibility required of the nanoscale R(I)TDs has been demanding and difficult to achieve. In this reported work, the design of TSRAM cells is approached from the perspective of maximising their yield and specific results are presented for an RITD-based cell. With advances in the control of semiconductor multilayer growth, it is shown that achieving acceptable yields is now within sight.
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