Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

Abstract

Conventional static random access memory (SRAM) suffers from high leakage power when implemented in advanced CMOS nodes, while modified bitcells or assist techniques are required to achieve robust low-voltage operation. Gain-cell eDRAM (GC-eDRAM) is an interesting area-efficient alternative to SRAM, but requires refresh cycles and typically a boosted write word-line (WWL). This brief proposes a hybrid GC-eDRAM/SRAM bitcell addressing the leakage power and low voltage robustness issues of SRAM, while avoiding bandwidth-consuming refresh and WWL boost of conventional GC-eDRAM. In the hybrid 8T bitcell, an SRAM keeper latch is connected to the storage node (SN) of a gain cell. The SRAM keepers are power gated most of the time for leakage reduction; the keepers are powered on only during zero bandwidth consuming refresh cycles, after write, and before read, to ensure strong data levels on the SN. Compared to a conventional 6T SRAM bitcell, the hybrid 8T bitcell has a 2T read port and an interruptible keeper for both robust read and write at low voltages. Simulations in 65-nm CMOS show that the hybrid bitcell enables 35% (at 400 mV) to 55% (at 1 V) lower data retention power than an 6T SRAM cell at 25 °C.