Yield-aware joint die packing, die matching and static thread mapping for hard real-time 3D embedded CMPs

Abstract

This paper addresses the problem of performance and thermal yield maximization for hard real-time 3D embedded chip multiprocessors. We propose a process variation-aware method that simultaneously performs die packing, die matching and static thread mapping by using design-time characteristics of the target hard real-time embedded application and the manufactured dies. To the best of our knowledge, this work is the first attempt to formulate die packing, die matching and static thread mapping as a single design-time yield maximization problem. Experimental results of applying our proposed method and several baselines on real-world benchmarks show that our method could achieve 27% yield improvement on average and up to 2.3x improvement at maximum compared to the best-performing baseline.