Workload Dependent Design and Power Modeling of Pattern Recognition Associative Memories

Abstract

In this work, we analyze and model the most significant parameters for the power consumption of a content addressable memory (CAM) based Pattern Recognition Associative Memory (PRAM) chip. Content Addressable Memories (CAMs) provide fast pattern search which is useful in a variety of applications. Their high speed comes from their parallel operation, which also results in high power consumption. In this study, we focus on their potential use in high energy particle physics experiments like at the LHC, to find and fit the tracks expected at the hardware trigger level. We find that common CAM blocks used in other applications like IP lookup are not fit for track fitting in high energy particle physics experiments due to the immensely different workload requirements. We identify these workload differences, which guide the design of the CAM blocks for specific workloads like tracking triggers. We show with tests on our prototype chip the high dependence of associative memory power consumption with the workload. We observe that the power consumption in the matchlines is highly dependent on the hit-rate of the workload; whereas the searchline power is influenced by the average Hamming distance between successive input data and is independent of the hit-rate. We also see that the dominant power consumption of associative memories, when used for tracking trigger applications, is in the searchlines instead of the matchlines. We present a simple power modeling strategy for these associative memories along with a description of the expected workload at the hardware trigger level of LHC, to guide future research on pattern recognition associative memory chips.