Low power RAM-based hierarchical CAM on FPGA

Abstract

Content Addressable Memories (CAMs) have been widely used to implement various high speed search functions in network devices such as routers and servers. In these devices, the role of CAM is to classify, drop or forward internet packets (i.e., packet classification). However, CAM suffers from several shortcomings such as high power consumption and low integration density. In addition, CAM is not available in most of modern Field Programmable Gate Array (FPGA), which has broad applications in network infrastructures. Therefore RAM-based CAM emulation has emerged as a promising alternative to CAM not only because RAM is a relatively mature technology but also due to the fact that there are more and larger RAM blocks on modern FPGA. In this paper, we propose a hierarchical search scheme for RAM-based CAM on FPGA. If a match is found in previous blocks, no subsequent search will be triggered and therefore average power consumption is reduced. Comparing with previous works which have not employed this technique, simulation results show that our method could reduce the power consumption up to 11.0% and 9.7% for block RAM based and distributed RAM based implementation respectively.