Wirebonding Based 3-D SiC IC Stacks for High Temperature Applications

Abstract

Current and past Venus landers can only operate on the planet’s surface for a few hours because the commercial silicon and compound semiconductor electronics fail to work in the extreme Venus surface environment of high temperature of 460°C and high carbon dioxide pressure of 9.4 MPa. Silicon carbide (SiC) integrated circuits (ICs) have been recently demonstrated to be able to withstand the simulated Venus surface-atmosphere environment for over 500 hours. SiC and GaN chips and sensors are promising for Venus surface exploration missions. To successfully implement the data collection and telemetry task, one needs to carefully package the SiC and GaN chips and sensor for them to be integrated into the Venus lander system. In the past several years, some preliminary research work has been done on the basic two-dimensional (2-D) packaging of SiC chips, including basic die attach and wire bonding. This paper discusses the wire bonding based 3-D SiC IC packaging to save the precious printed circuit board (PCB) footprint and improve the electrical and mechanical performance of the SiC IC package. High-temperature and high-pressure packaging materials and wirebond-based 3-D SiC IC packaging strategies are discussed to make the SiC chips and sensors work for an extended time. Stacked SiC chips are wire-bonded to the alumina substrate with screen-printed gold pads. The mechanical shear and electrical resistance tests are analyzed before and after the 3D SiC chip packages are subject to Venus simulation chamber tests. The SiC chips in the packages are expected to meet the high temperature Venus surface explorations missions for an extended time, i.e., days or months.