Edge-Controlled Mechanical Failure of Si and SiC Semiconductor Chips†

Abstract

Silicon (Si) and silicon carbide (SiC) semiconductor chips are subjected to thermal gradients during service, have coefficient of thermal expansion mismatches with the constituents they are attached to, and are therefore subjected to thermomechanical tensile stresses that can initiate their fracture. Because of inherent brittleness, their probabilistic (Weibull) tensile failure strength was examined to understand sustainable tensile stresses and any exhibition of strength-size-scaling. Failure stress testing of entire (10-mm-square) chips was conducted using uniaxial flexure (3-point-bending) and biaxial flexure (anticlastic bending). The advantage of the anticlastic bend test is all eight primary edges are subjected to identical sinusoidal stress distribution so tensile failure stress is concurrently sensitive to edge-state quality, surface-state quality, crystallographic orientation, and any strength anisotropies of any of those. Tensile stress tolerance of both Si and SiC chips was limited by extrinsic strength-limiting flaws located at their edges and on lapped surfaces too in the case of the Si. Both materials exhibited strength-size scaling; namely, a larger chip is likely to fail at a lower tensile stress. The anticlastic bend test method was effective for evaluating edge failure stress provided surface-type strength-limiting flaws were not dominant. Edge-strength anisotropy (i.e., crystallographic orientation dependence) was observed with both the Si and SiC chips. Surface-strength anisotropy also occurred with Si chips because one side was lapped and the other polished. Lastly, the SiC chips failed at much higher tensile stresses than Si chips; however, that strength difference could be a ramification of differences in edge-slicing quality and not necessarily from intrinsic material differences.