Wafer-level wet etching of high-aspect-ratio through silicon vias (TSVs) with high uniformity and low cost for silicon interposers with high-density interconnect of 3D packaging

Abstract

Silicon (Si) interposers have received an increasing amount of attention in microelectronic packaging industry due to its potential application in the emerging 2.5D system integration. One of the key steps in the fabrication flow of Si interposer is the formation of through silicon vias (TSVs), which enable the vertical communication of chips attached on either side of the interposer. Current method for TSVs formation suffers from high cost and low throughput. In this paper, we report successful TSVs formation by a novel wet chemical method, which is named as metal-assisted chemical etching (MaCE). In a typical experiment, fast etching of TSVs with 30 µm in diameter, 80 µm in pitch size, less than 50 nm in sidewall roughness and maximum depth of 330 µm on standard Si substrates is demonstrated. Effect of etching time, temperature of the etchant and application of external electric bias are discussed by comparative study. Uniformity of the TSVs array by MaCE is investigated. The results clearly demonstrate that MaCE is a promising method for TSVs formation on Si interposers with cost-efficiency and high throughput in large-scale manufacturing.