Wafer bonding type selection for 3D IC designs

Abstract

The minimization of TSV (through-silicon-via) count is one of the most important objectives in the 3D IC (three-dimensional integrated circuit) design. In this paper, we demonstrate that the selection of wafer bonding type for each pair of adjacent layers has a great impact on the TSV count. However, to the best of our knowledge, given a layer assignment result, the problem of selecting wafer bonding type for TSV count minimization has not been well studied. Based on that observation, we are motivated to use the network flow to formally model the problem and then use the shortest path approach to minimize the TSV count. Note that our shortest path approach guarantees solving this TSV count minimization problem optimally in polynomial time complexity. Compared with the previous high-level synthesis approach that only performs layer assignment to minimize the TSV count, benchmark data show that our approach can further reduce 48.38% TSV count through wafer bonding type selection.