Abstract
In quantum computing architectures, one important factor is the trade-off between the need to couple qubits to each other and to an external drive and the need to isolate them well enough in order to protect the information for an extended period of time. In the case of superconducting circuits, one approach is to utilize fixed frequency qubits coupled to coplanar waveguide resonators such that the system can be kept in a configuration that is relatively insensitive to noise. Here, we propose a scalable voltage-tunable quantum memory (QuMem) design concept compatible with superconducting qubit platforms. Our design builds on the recent progress in fabrication of Josephson field effect transistors (JJ-FETs) which use InAs quantum wells. The JJ-FET is incorporated into a tunable coupler between a transmission line and a high-quality resonator in order to control the overall inductance of the coupler. A full isolation of the high-quality resonator can be achieved by turning off the JJ-FET. This could allow for long coherence times and protection of the quantum information inside the storage cavity. The proposed design would facilitate the implementation of random access memory for storage of quantum information in between computational gate operations.
Highlights
Noisy intermediate-scale quantum computers are currently built on circuit quantum electrodynamics architectures, as well as trapped ions and neutral atoms
Quantum hardware with 50+ superconducting qubits takes the form of a quantum network with superconducting coplanar waveguide (CPW) resonators providing paths for microwave photons to indirectly interact with processing qubit nodes
The resulting memory modules can be integrated with circuit quantum electrodynamics (cQED) superconducting processors or other qubit platforms if efficient transduction is possible. This design uses a gate-tunable hybrid JJ-FET as the main element to tune the resonance frequency of a superconducting resonator. This voltage-tunable resonator would control the coupling between a feed-line and a superconducting storage cavity (SC)
Summary
Noisy intermediate-scale quantum computers are currently built on circuit quantum electrodynamics (cQED) architectures, as well as trapped ions and neutral atoms. There is a rich literature on the optimization of materials growth and resonator fabrication processes that recently led to resonator lifetimes of a few milliseconds [1]–[4] This progress has made superconducting resonators emerge as an integral part of the qubit system and as memory for quantum information. F f can limit the speed of quantum operations (increasing the length of quantum gates) This issue may be addressed by integrating tunable inductive elements into the resonators in order to drive them in and out of tune with various components within the circuit [5]. In the former, large arrays of qubits and resonators as quantum random access memory will be needed for short-term storage of the processed information [7]. Either of those approaches requires application of current directly to or near the chip causing excess energy dissipation and flux noise in the qubits
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