Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM

Abstract

In low supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {DD}}$ </tex-math></inline-formula> ), the wordline (WL) underdrive read assist and the negative bitline (NBL) write assist circuits are widely used for stable operation of SRAM. However, NBL consumes enormous energy and WL underdrive read assist degrades performance. A voltage-boosted fail-detecting circuit for selective write assist (VBFD-SWA) and selective cell current boosting (VBFD-SCCB) is proposed for high-density low-power FinFET static RAM (SRAM). VBFD-SWA detects the bitline status and then selectively triggers NBL only when a write failure is detected, reducing the write energy consumption. VBFD-SCCB detects slow bitcell and selectively triggers cell current boosting to improve read performance. The simulation results show that the write energy consumption is improved by 19% and the read performance is improved by 36% by applying the VBFD-SWA and VBFD-SCCB, respectively, with an area overhead of 10%.