Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique

Abstract

Voltage scaling is necessary to minimize power consumption. But the low voltages impede write in static random access memories (SRAMs). Condition is worsened when the periphery voltage is kept lower than the array voltage. Such nature of SRAMs at low voltages makes the use of write assist techniques inevitable. Negative bit line (NBL) technique proves to be the most efficient of all the assist techniques. But a large negative dip on bit line creates reliability issues. To cater for such issues, we propose a voltage sensitive write assist scheme for SRAM. This scheme enhances the NBL assist technique by restricting the negative dip at bit line to the required limit. This improves the device reliability by minimizing effects like hot carrier injection (HCI) and time dependent di-electric breakdown (TDDB). Design is implemented and simulated in 16nm bulk FinFET process for single port high density SRAM memory across the voltage range of 0.52V to 1.05V. All the simulations are done using HSPICE. Foundry spice models are used.