VLSI test through an improved LDA classification algorithm for test cost reduction

Abstract

During manufacturing test, more and more test patterns are required as the growing complexity of integrated circuits (ICs), resulting the test time increasing and consequently test cost. Aiming at the problem that test time is too long and the test pattern efficiency is affected, this study proposed an improved linear discriminant analysis (LDA) classification algorithm to select the valid test patterns (pattern that can make the test fail) only, so that the classification results can make the test cost reduction in logic circuit test. In addition, the valid test patterns can be selected in terms of polynomial regression function and to accomplish this, consequently convert the optimization problem into a mathematical function, so as to achieve broader adaptability. Experimental results demonstrate that the proposed method succeeds in saving 1.75 times test time compared with traditional methods. In addition, the proposed method outperformed the conventional test method in the hardware area/power/speed aspect.