Industrial practices of test cost reduction: Perspective, current design practices

Abstract

Summary form only given. Test cost is becoming increasingly significant percentage of COB (Cost of Build) in current SoCs (System-on-a-Chip). This is even critical in low cost markets like consumer devices. This session outlines test cost reduction strategy that can be adopted on a typical SoC. Strategy exploits known test cost reduction techniques that include DFT (Design-For-Test) techniques, target ATE (Automated Test Equipment) selection and statistical analysis on production data. DFT techniques discussed are multi-site, concurrent tests, scan compression, merged scan & memory IDDQ & retention and BIST (Built-in-Self-Test) solutions. In addition to impact of test cost reduction of these techniques, design overhead like gate count, robust power grid design, route-ability and diagnose-ability are discussed. These techniques also demand additional ATE resources like power supplies and analog resources which add to cost overhead. Product engineering techniques that are discussed are vector elimination based on statistical analysis of COF (Continue-on-Fail) data and program trimming techniques that include reducing tester overhead and removing unnecessary wait times. Impact to test quality (DPPM) is assessed with these techniques. Test cost impact of techniques described in this presentation is quantified based on data on a SOC, which is in production. Based on experience of test cost reduction activities, we propose a strategy for test cost reduction for a typical SoC that includes 2 step approach. Step-1 includes architectural techniques that will enable test time reduction in all test modes. Step-2 includes adopting test cost reduction techniques that are test mode specific. Test mode specific techniques are applied based on test cost distribution. Step-1: Architectural test cost reduction Multi-site remains the powerful test cost reduction architectural technique as it cuts down test time of all test patterns (or test modes). All limitations or challenges for designing for higher multi-site needs to be solved as part of test cost reduction. Low cost tester compliance is next most powerful technique as it directly affects (capital cost) test costs. Based on ATE, which is targeted for SoC, challenges due to limitations of low cost ATE are taken care in design. Step-2: Test cost distribution based test cost reduction The best way to plan test cost reduction strategy is identifying test modes that are major contributors to overall test time. This can be obtained from test time distribution chart. Based on test time distribution, each test mode is looked at for opportunities to reduce test time through one of techniques described in this paper.