Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs

Abstract

Test cost is becoming increasingly significant percentage of COB (Cost of Build) in current SoCs (System-on-a-Chip). This is even critical in low cost markets like consumer devices. This session covers test cost reduction strategy that can be adopted on a typical semiconductor product, during design and post-silicon phases. Test cost reduction during design phase includes, adoption of right DFT (Design-For-Test) architectures and technologies, target ATE (Automated Test Equipment) selection and design for compliance for targeted ATE. DFT architectural aspects that can impact test cost reduction are multi-site configuration, concurrent tests, scan compression technology, IDDQ strategy, memory test and repair solution. Critical challenges of these techniques and design impact like gate count overhead, robust power grid design, route-ability and diagnose-ability would be covered. The impact of these techniques is quantified at SOC level, from test cost point of view. Post-silicon test cost reduction techniques include approaches like vector elimination based on statistical analysis of COF (Continue-on-Fail) data and program trimming techniques to optimize test program. Vector elimination directly affects DPPM (Defective Parts Per Million) requirements and hence needs to be handled carefully. Another powerful post-silicon technique that can reduce test time and improve yield is adaptive test. Adaptive tests include techniques like a) on-line statistical sampling, which can selectively skip tests that statistically never fail b) outlier detection and extraction, which helps to eliminate expensive reliability tests like burn-in. Adaptive tests can also be used to improve the yield by off-setting tester parameters as per site2site variations and using fab PCM (Process Control Monitor) data to optimize the device for performance and power through appropriate trimming. As the design community is pushing for higher concurrent and higher compression goals, test power is becoming a major consideration. While EDA solutions like low power ATPG is prevalent in industry, comprehensive test power architecture advisor, which can guide designer to architect DFT solutions which is optimal from both test time and test power is the need of the industry. Current state of solution on this problem is covered in this session.