Abstract
Testing of Integrated Circuits (ICs) is essential for weeding out defects before the products are shipped to customers. With the growing complexity of ICs, high-cost specification tests are becoming a bottleneck owing to their lengthy Test Time (TT). TT becomes particularly critical when the overall costs of ICs have to be taken into consideration. Considering the problem that TT takes too long in the traditional test, i.e., a test with full Test Patterns (TPs), this paper proposes an improved K-Nearest Neighbor (KNN) algorithm to classify the defects, i.e., this TP selection approach utilizes a classification model to select the valid patterns only, to shorten the TT. Experimental results demonstrate that compared with the traditional method, the proposed method successfully reduces the TT by 1.75 times. Furthermore, the experimental results represent the optimal compromise between TC and Test Quality (TQ).
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