VLSI Implementation of Fully Parallel and CSD FIR Filter Architecture

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This paper proposes the VLSI implementation of Fully parallel and CSD FIR filter architecture. In this technique, the area and power optimization are achieved by the incorporation of Vedic multiplier and Koggstone adder instead of traditional multiplier and adder. Furthermore, a valid comparison of aforesaid architecture for 8-tap and 16-tap FIR filters is made in both linear and tree topology. Further, the proposed filter architecture is also analyzed in the presence of a pipeline mechanism. The VLSI implementation of the proposed FIR filter using Verilog HDL is carried out both in FPGA (Kintex -7 xc7k70tfbv676-1 family) and ASIC (180 nm technology) using Xilinx Vivado and Cadence Genus respectively. The FPGA implemented architecture consumes 1513 LUTs and 184 Slices for 8-tap and 16-tap, Similarly, the ASIC implementation occupies 93668 $\mu{\mathrm{m}}2$ area and 15.254 mW power.